Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-06-15
2003-02-11
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S113000, C327S202000, C327S298000
Reexamination Certificate
active
06518795
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally high-speed semiconductor devices and more specifically to a method and system for accessing a semiconductor device at multiple operating speeds.
BACKGROUND OF THE INVENTION
As it is the general trend to design and manufacture semiconductor devices that may operate at high speeds, high-speed semiconductor devices are becoming extremely prevalent in various applications. However, in some applications it is beneficial for a semiconductor device to operate at slower speeds than the typical operating speed of high-speed semiconductor devices. It is well known in the art to utilize a pipeline circuit to access data as a parallel activation according to the clock signal. In order to slow the effective operating speed of the semiconductor device, the clock latency of the semiconductor device may be reduced.
Reducing the clock latency of the semiconductor device has been accomplished by reducing the internal number of pipeline stages of the pipeline circuit. External mode changes are required to reduce the internal number of pipeline stages. Furthermore, reducing the clock latency may be restricted at various frequencies as clock periods of unused pipeline stages must match the original pipeline delay. Consequently, an improved system and method for accessing a semiconductor device at multiple operating speeds is required.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a novel system and method for accessing semiconductor devices at multiple operating speeds. In an embodiment of the present invention, access to a semiconductor device may be accommodated by a pipeline circuit configured to operate at a first operating speed while still providing access to the semiconductor device at multiple operating speeds without modification to the pipeline circuit. One example of the invention may be the utilization of an internal clock to control internal pipeline stages which may allow adjustment of an effective operating speed of a semiconductor device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 5619157 (1997-04-01), Kumata et al.
Chang Daniel
LSI Logic Corporation
Suiter & Associates PC
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