Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-05-14
2004-08-24
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S401000, C438S691000, C438S692000, C438S700000, C438S706000, C438S720000
Reexamination Certificate
active
06780775
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to lithographic processing of semiconductor devices and more particularly to a structure for lithographic alignment and a method for producing the same in a semiconductor process involving non-transparent layers.
BACKGROUND OF THE INVENTION
Semiconductor devices are continually becoming smaller in size and require manufacturing processes that are capable of producing these devices. Alignment techniques are implemented during manufacturing processes to ensure correct alignment of the various layers within semiconductor devices. Typically, alignment marks are utilized in the layers to help align the various features.
Magnetoresistive random access memory (MRAM) devices are typically processed using structures upon which are formed magnetic metal stacks. The magnetic stack consists of many different layers of metals and a thin layer of dielectric with a total thickness of a few tens of nanometers. The magnetic devices are built on top of the copper channels embedded in the inter-level dielectric (ILD) material. Since this stack is non-transparent to light, the lithography on top of this layer requires topographic features for alignment and overlay measurement marks on the layer. Typically this underlying layer has a chemical mechanical polish (CMP) finish. Forming the alignment marks is usually done by additional lithography and reactive ion etch (RIE) steps to generate marks on the CMP finished surface that exposes the copper and dielectric patterns. Additional RIE and subsequent clean steps boost cost and increase the chances of creating particles on the CMP finished level, however.
SUMMARY OF THE INVENTION
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by the present invention.
In a preferred embodiment structure of the present invention, the structure for alignment comprises a first metal layer having a top surface at a distance x below a top of the structure and a second metal layer extending from the top of the structure to a distance y below the top of the structure wherein the distance y is less than the distance x. A via is utilized to connect the first metal layer and the second metal layer. For alignment purposes, an alignment mark extending from the top of the structure to a depth of at least x is included. A non-transparent stack layer is deposited above the top of the structure with the stack layer conforming to the shape of the alignment mark whereby the alignment mark is visually recognizable.
A preferred method for producing a semiconductor device having and using an alignment mark comprises forming a first dielectric layer, etching a trench having predetermined dimensions into the dielectric layer, and depositing a first layer of metal into the trench. A second dielectric layer is formed over the first dielectric layer and over the first layer of metal and channels are etched into the second dielectric layer, at least one channel is used as a via extending to the first layer of metal. An opening is etched simultaneously with the channels into the second dielectric layer such that the opening extends through the second dielectric layer whereby a bottom surface of the opening is coplanar to a top surface of the first metal layer. The channels and the opening are filled and a remaining portion of the surface of the second dielectric layer is plated with metal. The filling step is controlled to fill the channels and to under fill the opening. Chemical mechanical polishing of the plate provides a planar surface on which a non-transparent stack of layers can be deposited. The non-transparent stack of layers conforms to the surface of the under filled opening during deposition of the non-transparent stack of layers resulting in an alignment mark on the non-transparent stack of layers.
One advantage of a preferred embodiment of the present invention is that it does not require additional RIE and subsequent clean steps that are costly and increase the chances of creating particles on the surfaces.
Another advantage of a preferred embodiment of the present invention is that the alignment of lithography on top of the non-transparent layer is made directly to the underneath metal layer. This reduces the overlay inaccuracy of introducing intermediate alignment marks that align to the metal and is then used as a reference to align the lithography on top of the non-transparent layer.
Another advantage of a preferred embodiment of the present invention is that the alignment mark does not take out additional space on the structure. Typically, additional lithography and etch steps would be needed to generate a new set of alignment marks that would require additional space on the chip.
A further advantage of a preferred embodiment of the present invention is that it decreases the chances of the metal becoming oxidized when it is exposed in the additional RIE steps.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
REFERENCES:
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6183614 (2001-02-01), Fu
patent: 6346454 (2002-02-01), Sung et al.
Chi-Tzung Wang. et al., Pad Wear Analysis in CMP; 1999 VMIC Conference: 1999 IMIC 109/99/0267(c).
Srini Raghavan, et al., Elecrochemical Behavior of Copper and Tantalum in Silica Containing Hydroxylamine. 1999 VMIC Conference: 1999 IMIC 109/99/0619(c).
Rajeev Bajaj. et al. Manufacturability Considerations and Approaches for Development of a Copper CMP Process: 1999 VMIC Conference: 1999 IMIC 109/99/0144(c).
Infineon - Technologies AG
Slater & Matsil, L.L.
Vinh Lan
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