Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-10-20
2001-07-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S041000, C326S047000, C326S101000
Reexamination Certificate
active
06260184
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to the design of integrated circuit devices and, more particularly, to the design of an integrated circuit device by selectively reducing or maintaining power lines of the device.
BACKGROUND OF THE INVENTION
Integrated circuit devices are formed from a large number of interconnected integrated circuits. The active elements or transistors which make up the integrated circuits are typically fabricated in the lower layers of the integrated circuit device. Above the transistors, a number of metal layers are formed. The metal layers are used as power lines, which provide power to the integrated circuits, and as signal wires, which interconnect the integrated circuits and provide signal transmission therebetween.
During integrated circuit design, design engineers pay particular attention to the allocation of the metal layers between power lines and signal wires in order to ensure adequate power while achieving the most densely packed signal wiring. In a typical design approach, a software model containing the integrated circuits of the device is first developed using well known design techniques. The design engineer then develops a power line layout or grid for the modeled integrated circuit device. The power line layout is typically designed with moderate conservatism in order to ensure adequate power for the device. Next, signal wires are added to the integrated circuit model based on the layout of the integrated circuits on the device as well as the power line layout. Typically, the signal wires are automatically routed using software routing tools (hereinafter “routers”), such as G-Route™ by Cadence Design Systems, Inc.
The routing of signal wires typically includes two phases: a global phase and a detail phase. In the global phase, the router divides the entire integrated circuit device into squares or tiles, each of which contain a number of tracks in which signal wires may be routed. Using the global tiles the router generates, paths which interconnect the integrated circuits.
FIG. 1A
illustrates an exemplary portion
100
of an integrated circuit device divided up into tiles
110
and having two circuits A and B interconnected by a global path
120
. In the detail phase, the router makes detailed signal wire routes between integrated circuits based on the global paths and the tracks of the tiles therein.
FIG. 1B
illustrates a signal wire
130
interconnecting circuits A and B after the detailed phase of wire routing. In some instances, after automatically routing signal wires, some routes between circuits will remain incomplete. These incomplete routes are then typically completed manually.
The above approach places significant limitations on the scaling of integrated circuit devices. For example, should an excessively conservative amount of metal be devoted to power lines, the integrated circuits may need to be spread out in order provide room for the signal wires. Spreading out of the integrated circuits increases the size of the device and may also negatively impact performance.
SUMMARY OF THE INVENTION
The present invention provides a system and method for designing an integrated circuit device by selectively reducing or maintaining power lines of the device. This can, for example, allow for more efficient allocation of power lines and signal wires and increase the density of the chip.
In accordance with one embodiment of the invention, a method of designing an integrated circuit device is provided. In this method, a power demand value of a region of the device is determined and a wiring demand value of the region of the device is determined. Based on the wiring demand value and the power demand value, power lines in the region are selectively maintained or reduced. These steps may be repeated for each region of the device and a new power line layout may be generated after stepping through each of the regions.
A system, in accordance with another embodiment of the invention, includes a power module, a wiring module, and a power line module. The power module determines power demand values for locations of the device. The wiring module determines wiring demand values for locations of the device. The power line module selectively maintains or reduces power lines in a region of the device based on a wiring demand value and a power demand value of the region. The wiring demand value of the region is based the wiring demand values of one or more locations of the device and the power demand value of the region is based on the power demand values for one or more locations of the device.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures in the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 4698760 (1987-10-01), Lembach et al.
patent: 5880967 (1999-03-01), Jyu et al.
patent: 5917729 (1999-06-01), Naganuma et al.
patent: 5926397 (1999-07-01), Yamanouchi
patent: 5949689 (1999-09-01), Olson et al.
patent: 6083271 (2000-07-01), Morgan
patent: 6090151 (2000-07-01), Gehman et al.
Chao et al, “Floorplanning for Low Power Designs”, IEEE International Symposium, vol. 1, pp. 45-48, 1995.*
Shepard et al., “Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessors,” vol. 41, No. 4/5, IBM J. Res. Develop., Jul./Sep. 1997, pp. 515-547.
Brennan Thomas C.
Rohn Michael
International Business Machines - Corporation
Merchant & Gould
Smith Matthew
Speight Jibreel
Truelson Roy W.
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