Design methodology of guard ring design resistance...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

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07549135

ABSTRACT:
A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS circuit and the corresponding power supply. By comparing the calculated guard ring to power supply path resistance value to resistance criteria derived from specifications, elements that need further redesign are identified. Repeated redesign with several redesign options eventually lead to an optimized guard ring structure that provides area-efficient and sufficient latchup protection for the CMOS circuit.

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Ker, Ming-Dou, et al., “Automatic Methodology for Placing the Guard Rings into Chip Layout to Prevent Latchup in CMOS IC's”, IEDM Tech. Dig., 2001, pp. 113-116.
Harame, D. L., et al., “Design Automation Methodology and RF/Analog Modeling for RF CMOS and SiGe BiCMOS Technologies”, IBM J. Res. & Dev., vol. 47, No. 2/3, Mar./May 2003.

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