Design methodology for MuGFET ESD protection devices

Details Design methodology for MuGFET ESD protection devices Design methodology for MuGFET ESD protection devices

2011-04-12

2011-04-12

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

With measuring or testing

C438S135000, C438S157000, C438S283000

Reexamination Certificate

active

07923266

ABSTRACT:
A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (Wfin), gate length (LG) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.

REFERENCES:
Russ, Christian C. et al., “ESD Evaluation of the Emerging MuGFET Technology”, IEEE Transactions on Device and Materials Reliability, vol. 7, No. 1, Mar. 2007, pp. 152-161.
Lee, Chi-Woo et al., “Device Design Guidelines for Nano-Scale MuGFETs”, Solid-State Electronics, vol. 51, No. 3, Mar. 30, 2007, pp. 505-510.
Yim, Daebin et al., “Layout Optimization of ESD Protection TFO-NMOS by Two-Dimensional Device Simulation”, Simulation of Semiconductor Processes and Devices, International Conference on Cambridge, MA, Sep. 8-10, 1997, pp. 29-31.
Khazhinsky, Michael G. et al., “Comprehensive ESD Protection Approach in Advanced CMOS SOI Technologies”, Journal of Electrostatics, vol. 64, No. 11, Oct. 1, 2006, pp. 720-729.
Shigyo, N. et al., “ESD Protection Device Design Using Statistical Methods”, Solid-State Electronics, vol. 46, No. 12, Dec. 1, 2002, pp. 2117-2122.
European Search Report, European Patent Application 09159669.2 dated Jul. 27, 2009.
Scholz et al., “Calibrated Wafer-Level HBM Measurement for Quasi-Static and Transient Device Analysis,” EOS/ESD Symposium 07-89.
Tremouilles et al., “Understanding the Optimization of Sub-45nm FinFET Devices for ESD Applications,” EOS/ESD Symposium 07-408.
Augendre et al., “On the Scalability of Source/Drain Current Enhancement in Thin Film sSOI,” 2005 IEEE, p. 301-304.
Collaert et al., “Multi-gate Devices for the 32nm Technology Node and Beyond,” 2007 IEEE, p. 143-146.
Choi et al., “Large Scale Integration and Reliability Consideration of Triple Gate Transistors,” 2004 IEEE.
Hoffman et al., “GIDS (Gate-Induced Drain Leakage) and Parasitic Schottky Barrier Leakage Elimination in Aggressively Scaled HfO2/TiN FinFET Devices,” 2005 IEEE.
“Physical Origin of Negative Differential Resistance in SOI Transistors,” Electronic Letters 22nd Jun. 1989, vol. 25, No. 13, p. 827-828.
Fuiwara et al., “Impact of BOX Scaling on 30 nm Gate Legth FD SOI MOSFETs,” 2008 IEEE, p. 180-182.
Parvais et al., “Analysis of the FinFET Parasitics for Improved RF Performances,” IEEE 2007, p. 37-38.
Wu et al., “Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETSs,” IEEE Transactions on Electron Devices, vol. 54, No. 4, Apr. 2007.
The International Technology Roadmap for Semiconductors: 2007, Table FEP2b Starting Materials Technology Requirements-Long-Term Years.
Collaert et al., “Multi-Gate Devices for the 32nm Technology Node and Beyond: Challenges for Selective Epitaxial Growth,” Think Solid Films 517 (2008) 101-104.
Collaert et al., “Multi-Gate Devices for the 32nm Technology Node and Beyond: Challenges for Selective Epitaxial Growth.”
Collaert et al., “Tall Triple-Gae Devices with TiN/HfO2 Gate Stack,” 2005 Symposium on VLSI Technology Digest of Technical Papers, p. 108-109.
European Search Report, European Patent Application No. 08156029.4, dated Aug. 27, 2008.
Shigyo, N. et al., “ESD Protection Device Design Using Statistical Methods”, Solid State Electronics, Elsevier Science Publishers, vol. 46, No. 12, Dec. 1, 2002, pp. 2117-2122.
Trémouilles, D. et al., “Understanding the Optimization of Sub-45nm FinFET Devices for ESD Applications”, 29th Electrical Overstress/Electrostatic Discharge Symposium, 2007, XP002488347, pp. 7A.5-1-7A.5-8.
Khazhinksy, Michael G. et al., “Comprehensive ESD Protection Approach in Advanced CMOS SOI Technologies”, Journal of Electrostatics, Elsevier Science Publishers, vol. 64, No. 11, Oct. 1, 2006, pp. 720-729.
Yim, Daebin et al., “Layout Optimization of ESD Protection TFO-NMOS by Two-Dimensional Device Stimulation”, Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97, International Conference on Cambridge, MA, USA, Sep. 8, 1997, pp. 29-31.
Lee, Chi-Woo et al., “Device Design Guidelines for Nano-Scale MuGFETs”, Solid-State Electronics, Elsevier Science Publishers, vol. 51, No. 3, Mar. 30, 1997, pp. 505-510.

Affiliated with

Also associated with

Rating

Design methodology for MuGFET ESD protection devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design methodology for MuGFET ESD protection devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design methodology for MuGFET ESD protection devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2736575