Design methodology for inserting RAM clock delays

Details Design methodology for inserting RAM clock delays Design methodology for inserting RAM clock delays

2000-08-21

2003-06-03

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06574781

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of designing a semiconductor integrated circuit, this method constituting one part of the general field of semiconductor integrated circuit fabrication technology.
Large-scale integrated circuits are now designed through the use of computer-aided design (CAD) tools, also referred to as electronic design automation (EDA) tools. In the past, such tools were based on the input of schematic circuit diagrams, but recent tools synthesize the circuit design from an abstract description of the desired circuit functions, entered not in diagrammatic form but in a hardware description language (HDL). These tools also generate a clock tree that supplies clock signals to the parts of the integrated circuit that require clock input. In generating the clock tree, the tools automatically balance the clock tree and minimize clock skew, so that the clock signals supplied to different parts of the integrated circuit are mutually synchronized.
Among the parts of a large-scale integrated circuit there may be one or more embedded random-access memory (RAM) modules, also referred to as RAM macrocells. In the past, RAM was asynchronous, not requiring input of a clock signal, and not constrained by clock timing. As circuit speeds have increased and circuit dimensions have decreased, however, asynchronous RAM has given way to synchronous RAM, which operates in synchronization with a clock signal supplied through the clock tree. The use of synchronous RAM greatly simplifies the timing design of RAM control signals, but raises a new problem, in that at high clock speeds, RAM set-up timing requirements become difficult to satisfy.
In a typical read access to an embedded synchronous RAM macrocell, for example, output of an address signal to the RAM macrocell begins at a falling transition of the clock signal, and the address signal is latched at the next rising transition of the clock signal. This leaves at most only one-half of one clock cycle of address set-up time. To aggravate the problem, the processing unit that generates the address signal may be located at some distance from the RAM macrocell, causing the address signal to be delayed in propagation, so the address set-up time may be considerably less than one-half clock cycle. Depending on the propagation delay, the RAM address set-up time may be inadequate.
If the integrated circuit were designed by input of schematic diagrams, RAM set-up timing problems could be dealt with by manual insertion of delay elements in the RAM clock line. With tools that generate the clock tree automatically, however, such timing problems are not easily solved, because the tools automatically ensure that the clock tree supplies substantially synchronized clock signals to processing units and RAM macrocells alike.
Further explanation of the RAM set-up timing problem will be given in the detailed description of the invention.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an adequate set-up time for a RAM macrocell embedded in an integrated circuit designed by tools that automatically generate a clock tree with minimal clock skew.
The invented method of designing a semiconductor integrated circuit including a RAM macrocell uses computer-aided design tools that automatically generate a clock tree. The clock tree includes a clock path having a root cell at which a clock signal is generated, a leaf cell disposed in the RAM macrocell, and one or more buffers disposed between the root cell and the leaf cell. After the clock tree is generated, the computer-aided design tools are used to modify the clock tree so as to increase the clock propagation delay on the clock path from the root cell to the RAM macrocell.
In one aspect of the invention, the clock tree is modified by designating one of the buffers on the clock path from the root cell to the RAM macrocell as a leaf cell, in place of the leaf cell in the RAM macrocell, and then using the computer-aided design tools to regenerate the clock tree.
In another aspect of the invention, the clock tree is modified by down-sizing a buffer on the clock path from the root cell to the RAM macrocell; that is, by reducing the dimensions of transistors in the buffer, using the computer-aided design tools, thereby reducing the current-driving capability of the buffer.
By delaying the clock signal supplied to the RAM macrocell, the invented method can usually provide an adequate set-up time for the RAM macrocell, while still permitting the clock tree to;be generated entirely by use of the computer-aided design tools.


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