Design methodology for dummy lines

Details Design methodology for dummy lines Design methodology for dummy lines

2005-11-01

2005-11-01

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C430S005000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06961915

ABSTRACT:
A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

REFERENCES:
patent: 5108945 (1992-04-01), Matthews
patent: 5965940 (1999-10-01), Juengling
patent: 5981384 (1999-11-01), Juengling
“Chip-Level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films”, Liu, George Y. et al., Feb. 11-12, 1999, CMP-MIC Conference, pp. 120-127.

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