Design method of logic circuit using data flow graph

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06968523

ABSTRACT:
An algorithm of a logic circuit is converted from an operation description having operators into a data flow graph having operation nodes executing the operators arranged in order of the executing. Execution steps are allocated in the data flow graph, and registers storing output data from the operation nodes are inserted after execution of the execution steps. A data path of the logic circuit having operation units which served as the operation nodes and storage elements which served as the registers, and control information on the data path are produced. An operator/operation unit database configured to retrieve the operation units executing the operators from the operators and configured to retrieve the operators outputting data stored in the registers which served as the storage elements from the execution steps and the storage elements are produced.

REFERENCES:
patent: 5175843 (1992-12-01), Casavant et al.
patent: 5706205 (1998-01-01), Masuda et al.
patent: 6237125 (2001-05-01), Masuda et al.
Dr. Sreenivasa Rao, et al., “Partitioning by Regularity Extraction”, 29thACM/IEEE Design Automation Conference, Jun. 8-12, 1992, pp. 235-238.

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