Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-02
2004-08-31
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06785876
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a design method for a semiconductor integrated circuit device including a plurality of circuits having a plurality of functions.
In recent years, a concept of system LSI constructed of a plurality of LSI circuits formed on a common substrate has been raised, and various design techniques for system LSI have been suggested. An advantage of the system LSI is that memories such as DRAMs, logic LSI circuits, and analog circuits such as high-frequency circuits can be incorporated in one semiconductor device, to attain semiconductor devices of various types and functions in exceedingly high integration.
In design of the conventional system LSI described above, design properties called cores or intellectual properties (IPs) are often used. Such cores are independently designed. Therefore, when the cores are united into a device, smooth operation may not necessarily be secured. In order to design a system that can secure smooth operation, however, enormous amounts of time and effort are actually required since the respective cores or IPs are black boxes.
SUMMARY OF THE INVENTION
An object of the present invention is providing a design method for a semiconductor integrated circuit device in which optimization is facilitated by providing a means of permitting flexible selection of IPs while the consistency of the function of the IPs is maintained.
The first design method for a semiconductor integrated circuit device of the present invention includes the steps of: (a) storing a plurality of IPs common in function in a memory for each of a plurality of functions; (b) constructing a function group structure for satisfying a certain specification; and (c) selecting and retrieving one IP from the plurality of IPs common in function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure.
By the above method, it is possible to store a plurality of IPs common in function in a library and select an appropriate IP for each function. This ensures the consistency of the function irrespective of a change of the IP, and thus the time required for design, which is conventionally long, can be reduced to a minimum.
The above design method may further include the step of: (e) for each function, dividing an object implementing the function so that the object is mapped to a hardware (HW) model and a software (SW) model of architecture models in a database. This enables design of an optimized semiconductor integrated circuit device.
The above design method may further include the step of: (d) expanding the IP hierarchically into functional blocks after the step (c), wherein in the step (e), for each of the functional blocks obtained by the expansion, an object implementing the functional block is mapped to a HW model and a SW model of architecture models. This enables design of a further optimized semiconductor integrated circuit device.
The second design method for a semiconductor integrated circuit device of the present invention includes the steps of: (a) storing a plurality of IPs each having a function in a memory; (b) constructing a function group structure for satisfying a certain specification; (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure; (d) expanding the IP hierarchically into functional blocks; and (e) for each of the functional blocks obtained by the hierarchical expansion, dividing an object implementing the functional block so that the object is mapped to a HW model and a SW model of architecture models in a database.
By dividing the IP into a HW model and a SW model after the IP is hierarchically expanded as described above, mapping can be performed separately for the HW model and the SW model for the IP. This enables design of a more optimized system compared with the mapping for the IP as a unit.
In the step (e), static analysis considering overlap of an area may be performed for HW portions of the functional blocks. This improves the precision of estimation of the area.
The above design method may further include the step of: (f) performing dynamic performance analysis for determining the mapping of each functional block in the function group structure to a HW model and a SW model after the step (e). This improves the precision of the analysis.
The database preferably stores a SW model having a function equivalent to HW for each function of the HW.
In the step (f), the mapping of each functional block to a HW model and a SW model may be switched so that the power consumption is kept from exceeding an upper limit along the time axis.
In the step (f), also, when the load rate of CPU obtained when a functional block is mapped to HW is below a certain lower limit, the mapping of the functional block may be switched to SW.
In the step (e), analysis considering power consumption of a memory may be performed.
The third design method for a semiconductor integrated circuit device of the present invention includes the steps of: (a) storing a plurality of HW models in a memory as architecture models; and (b) retrieving architecture models from the memory as a model group to construct an architecture satisfying a certain specification from the model group, wherein in the step (b), the architecture is constructed so that the model group includes a plurality of buses and a bus bridge model for connecting the buses.
By providing a plurality of buses as described above, it is possible to construct an architecture suitable for a structure having a semiconductor interconnection substrate, such as an IPOS device.
In the step (b), the bus bridge model may connect two buses having different widths in a manner of adjusting the bus widths and the data transfer speeds. This enables smooth data transfer in the case where the bus widths and the data transfer speeds of two buses connected to the bus bridge model are different from each other, for example.
The fourth design method for a semiconductor integrated circuit device of the present invention includes the steps of: (a) storing a plurality of HW models in a memory as architecture models; (b) retrieving architecture models from the memory as a model group to construct an architecture satisfying a certain specification from the model group, (c) constructing a function group structure for satisfying the certain specification; (d) providing test benches on input and output sides of the function group structure; and (e) mapping functions in the function group structure and the test benches to the models in the architecture.
By the above method, a test bench can be mapped to HW. This enables use of parameters such as the time required for input/output at the test bench in the performance analysis and the like.
In the step (a), the plurality of models may include an interface (I/F) model, and in the step (b), the architecture may be constructed so as to include an I/F model in the model group. This enables optimization of a system in consideration of signal delay and power consumption at the I/F model handling input/output signals.
In the step (e), the test bench on the input or output side may be mapped to the I/F model in the architecture. Thus, the test bench, which is conventionally handled as a mere input signal, is mapped to an I/F model as HW. This enables analysis of the processing time considering delay and analysis of power consumption considering operation of the I/F model, in the subsequent performance analysis. In other words, analysis precision can be improved.
In the step (a), the plurality of models may include a memory. In the step (b), the architecture may be constructed so as to include a memory in the model group, and in the step (e), the test bench on the input or output side may be mapped to the memory in the architecture.
The fifth design method for a semiconductor integrated circuit device of the present invention includes the steps of: (a) storing a plur
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