Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-24
2006-01-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06990642
ABSTRACT:
The present invention provides a method for designing LSI including a logic circuit equipped with a scan circuit without generating a hard-macro library for the scan flip flops constituting the scan circuit. According to the method, first netlist NL1is converted into second netlist NL2by adding scan circuit including scan flip-flops. Order data for connecting scan chain of the scan circuit is extracted from the second netlist NL2. Such second netlist NL2is converted into third netlist NL3including only hard-macros, and the third netlist NL3is laid-out by re-ordering the scan chain so that the newly generated order data for is stored temporally. Fourth netlist NL4including scan circuit formed by scan flip-flops of soft-macros is generated on the basis of the stored order data, then the fourth netlist NL4is converted into fifth netlist NL5by substituting the scan flip-flops of soft-macros for standard cells of hard-macros. Finally the generated fifth netlist is laid-out without re-ordering the scan chain.
REFERENCES:
patent: 5828579 (1998-10-01), Beausang
patent: 5949692 (1999-09-01), Beausang et al.
patent: 6301688 (2001-10-01), Roy
patent: 6434733 (2002-08-01), Duggirala et al.
patent: 2004/0015788 (2004-01-01), Huang et al.
Fujitsu Limited
Siek Vuthe
Staas & Halsey , LLP
Tat Binh
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