Design method for essentially digital systems and components...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07124377

ABSTRACT:
The present invention relates to the design of essentially digital systems and components. In one embodiment, a parameterized model of a sub-component of an essentially digital system is provided. This sub-component is used in components of the system, e.g. interconnect at the different levels (up to the packaging level) and includes all relevant parameters with their physical constraints. If certain parameters do not play a significant role at the system level exploration, they can be left out of the exploration. But then they should preferably be fixed on the value that allows the cheapest and most reliable process technology solutions (independent of their delay or energy consequences). For the parameters that do have a large impact, the subranges of their trade-off curves, especially Pareto curves, that are appropriate for a given target domain (e.g. ambient multimedia) should be carefully selected to match design cost, process cost and reliability issues.

REFERENCES:
patent: 5870313 (1999-02-01), Boyle et al.
patent: 2005/0022141 (2005-01-01), Walker et al.
patent: 2005/0149898 (2005-07-01), Hakewill et al.
patent: 2005/0204316 (2005-09-01), Nebel et al.
patent: 2005/0251771 (2005-11-01), Robles
B.Amrutur et al. “Speed and Power Scaling of SRAM's”, IEEE Journal of Solid-state Circ., vol. 35 No. 2, pp. 175-185, Feb. 2000.
E.Brockmeyer et al. “Systematic Cycle budget versus System Power Trade-off: a New Perspective on System Exploration of Real-time Data-dominated Applications”, Proc. IEEE Intnl. Symp. on Low Power Design, Rapallo, Italy, pp. 137-142, Aug. 2000.
J.A.Davis et al. “Interconnect limits on gigascale integration (GSI) in the 21st century”, Proc. of the IEEE, No. 3, vol. 89, pp. 305-324, Mar. 2001.
R.Ho et al. “The future of wires”, Proc. Of the IEEE, vol. 89, No. 4, pp. 490-504, Apr. 2001.
K.Itoh et al., “Limitations and challenges of multi-gigabit DRAM chip design”, IEEE J. of Solid-state Circ., vol. 32, No. 5, pp. 624-634, May 1997.
D.Sylvester et al., “Impact of small process geometries on microarchitectures in systems on a chip”, Proc. of the IEEE, vol. 89, No. 4, pp. 467-489, Apr. 2001.
A. Vandecappelle et al., “Global Multimedia System Design Exploration using Accurate Memory Organization Feedback” Proc. 36th ACM/IEEE Design Automation Conf., New Orleans LA, pp. 327-332, Jun. 1999.
S.J.E.Wilton et al., “CACTI: An enhanced cache access and cycle time model”, IEEE J. of Solid State Circuits, vol. 31, No. 5, pp. 677-688, May 1996.
S. Wuytack et al., “Minimizing the Required Memory Bandwidth in VLSI System Realizations”, IEEE Trans. on VLSI Systems, vol. 7, No. 4, pp. 433-441, Dec. 1999.
R. J. Evans et al.,Energy Consumption Modeling and Optimization for SRAM's,IEEE Journal of Solid-State Circuits, vol. 30, No. 4, pp. 571-579, May 1995.
T. Seki et al.,A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier,IEEE Journal of Solid-State Circuits, vol. 28, No. 4, pp. 478-483, Apr. 1993.
A. P. Chandrakasan et al., “Low-Power CMOS Digital Design”,IEEE Journal of Solid-State Circuits, No. 4, vol. 27, pp. 473, Apr. 1992.
J. Lachman et al., “A 500MHz 1.5MB cache with on-chip CPU”, Proceedings of the ISSC Conference (1999) p. 192.
A. Chandrakasan et al., “A Low Power Chipset for Portable Multimedia Application”, (1994) IEEE International Solid-State Circuits Conf., pp. 82-83.
A. Papanikolaou et al., “Interconnect Exploration for Future Wire Dominated Technologies” (2002).
http://research.compag.com/wrl/people/jouppi/Cacti.h, “Cacti”, Accessed prior to Apr. 4, 2003 and retrieved after Apr. 2, 2004.
Rambus, “Gigahertz Rambus Signaling Technologies” (2001) pp. 1-4.
http://www.research.compaq.com/wrl/projects/memorySystems/m, “Memory System Project”, (2000) pp. 1-3.
Sylvester et al., “Getting to the Bottom of Deep Submicron II: A Global Wiring Paradigm”, (1999).
Doug Matzke, “Will Physical Scalability Sabotage Performance Gains?”, (1997), pp. 37-39.
Arden et al., “International Technology Roadmap for Semiconductors” (2001).
Brockmeyer E et al: “Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications” Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on Jul. 26-27, 2000, Piscataway, NJ, USA,IEEE, Jul. 26, 2000, pp. 137-142, XP010517318 ISBN: 1-58113-190-9.
Givargis T et al: “System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip” IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No. O1CH37281) IEEE Piscataway, NJ, USA, Nov. 8, 2001, pp. 25-30, XP002323201 ISBN: 0-7803-7247-6.
Grun P et al: “Memory system connectivity exploration” Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibiton IEEE Comput. Soc Los Alamitos, CA, USA, Mar. 4, 2002, pp. 894-901, XP002323202 ISBN: 0-7695-1471-5.
Papanikolaou A et al: “Global Interconnect Trade-off For Technology Over Memory Modules To Application Level: Case Study” Int. Workshop Syst. Level Interconnect Predict.; International Workshop on System Level Interconnect Prediction 2003, 2003, pp. 125-132, XP002323252.
Papanikolaou A et al: “Interconnect Exploration for Future Wire Dominated Technologies” Int. Workshop Syst. Level Interconnect Predict.; International Workshop on System Level Interconnect Prediction 2002, 2002, pp. 105-106, XP002323203.
Yunsi Fei et al:“Functional partitioning for low power distributed systems of systems-on-a-chip” Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings. Bangalore, India Jan. 7-11, 2002, Los Alamitos, CA, USA, IEEE Comput. Soc, US, Jan. 7, 2002, pp. 274-281, XP010588114 ISBN: 0-7695-1441-3.

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