Design method, design apparatus, and computer program for...

Details Design method, design apparatus, and computer program for... Design method, design apparatus, and computer program for...

2005-11-18

2010-06-01

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07730431

ABSTRACT:
The relative placement orders of cells with respect to circuit diagram information received are automatically determined, and the cells are automatically placed in relative positional relationships according to the placement orders given to the circuit diagram information.

REFERENCES:
patent: 2003/0237072 (2003-12-01), Melli et al.
patent: 2004/0003366 (2004-01-01), Suzuki
patent: 2004/0243963 (2004-12-01), Srinivasan et al.
patent: 2006/0080629 (2006-04-01), Sampath
patent: 5-326704 (1993-12-01), None
patent: 9-246388 (1997-09-01), None
patent: 10-21272 (1998-01-01), None
patent: 10-74842 (1998-03-01), None
patent: 10-92941 (1998-04-01), None
patent: 10-189750 (1998-07-01), None
patent: 2800781 (1998-07-01), None
patent: 11-111846 (1999-04-01), None
patent: 2001-68551 (2001-03-01), None
patent: 3256597 (2001-11-01), None
patent: 3433025 (2003-05-01), None
Machine Translation of Japanese Publiccation No. 5-326704 to Suzuki Goro, Semiconductor Layout Designing Method and Device Thereof, date of publication: Oct. 12, 1993, 1 cover page and 24 content pages.

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