Design method and system for providing transistors with...

Details Design method and system for providing transistors with... Design method and system for providing transistors with...

2001-10-25

2003-07-22

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06598214

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to electronic circuits and are more particularly directed to designs for circuits including a number of metal oxide semiconductor (“MOS”) transistors and to optimize drive current capability versus area consumption and capacitance load.
Semiconductor devices have become prevalent in all aspects of electronic circuits, and the design of transistors used in such circuits typically takes into account various factors including layout area, power consumption, speed, and the like. Various computer-assisted design systems have arisen and many of these systems attempt to consider and optimize the above factors in developing circuit designs. These systems are able to increase the efficiency of circuit design, and the systems themselves are periodically improved which may therefore also improve the circuit designs resulting from the system. Indeed, the preferred embodiments discussed later form a basis to improve such systems as well as circuit design either by itself or as a result of such an improved computer-assisted design system.
By way of further background,
FIG. 1
illustrates a plan view of a prior art transistor
10
in order to establish various terminology and related aspects to be used throughout this document. Transistor
10
is typically formed in connection with an underlying semiconductor substrate, although such a substrate is not visible from the plan perspective in
FIG. 1. A
semiconductor active region is defined relative to the substrate, such as by forming isolating regions
12
1
, and
12
2
, thereby defining the active region as the semiconductor area accessible at the upper semiconductor surface and between the isolating regions. Isolating regions
12
1
and
12
2
may be formed using shallow trench isolation (“STI”) or other isolating techniques (e.g., field oxides), and while shown in
FIG. 1
as separate regions they also may be a continuous region all around the perimeter of the active region. A gate G
1
is formed, typically by patterning and etching a formed layer of polycrystalline silicon (“polysilicon”) that is formed over the semiconductor substrate. In effect, gate G
1
separates the active region into two areas generally to the sides of gate G
1
and in which the source and drain of transistor
10
are formed. In many transistor configurations, the source and drain are physically alike and symmetric. Further, they also may be electrically connected so that for different instances current flow changes directions. Thus, for sake of general reference and unless specified otherwise, each such region is referred to as a source/drain in FIG.
1
and there is a source/drain S/D
1
and a source/drain S/D
2
. Typically, source/drains S/D
1
and S/D
2
are formed by implanting dopants adjacent both edges of gate G
1
and into the active region (where the active region may include one or more wells previously formed within the substrate). For example, for an n-type MOS transistor (“NMOS”), each source/drain S/D
1
and S/D
2
is formed by one or more implanting steps that implant n-type dopants, where these dopants are often self-aligned to gate G
1
(and possibly to insulating sidewalls formed along gate G
1
, although such sidewalls are not shown to simplify the Figure and discussion). For each source/drain S/D
1
and S/D
2
, a number of contacts are formed so that electrical access may be made to the respective source/drain. By way of reference and example in
FIG. 1
, these contacts are C
1
through C
4
with respect to source/drain S/D
1
, and these contacts are C
5
through C
8
with respect to source/drain S/D
2
. The techniques for forming contacts C
1
through C
8
may take various forms. Finally, note that gate G
1
includes an electrical contact pad CP
1
formed by extending the conductive gate material beyond the perimeter of the active region.
FIG. 1
further defines various dimensions which are noteworthy in prior art circuit design. First, in the dimension that gate G
1
separates the active region into source/drains S/D
1
and S/D
2
, and to the extent that gate G
1
overlies the active region (i.e., as shown vertically in FIG.
1
), is the width of gate G
1
, designated W
g
. Note that gate G
1
may extend beyond the active region such as shown in
FIG. 1
in the vertical dimension, but the gate width W
g
is defined only where the gate overlies the active region. Second, in the dimension that gate G
1
is perpendicular to W
g
is the length of gate G
1
, designated L
g
. Often, L
g
and W
g
are established by a circuit designer, either manually or by a computer-assisted technique such as with a special design program used to develop transistor inclusive circuits. Moreover, as technology advances, the gate length L
g
commonly decreases, and often there is a corresponding decrease in W
g
. Indeed, in some contemporary circuits, a so-called set of design rules are established and which sets minimum limits to certain critical dimensions. Each transistor in the circuit is constructed such that these design rules are not violated by a dimension falling below any of the minimum limits. For example, under contemporary designs a typical set of design rules may dictate a minimum value of L
g
=0.11 &mgr;m and that for W
g
=0.15 &mgr;m.
FIG. 1
introduces two additional distances by way of further background to the preferred embodiment. Specifically, within each source/drain, each contact C
1
through C
8
is located in a position relative to gate G
1
and relative to the outer perimeter, or edge, of the active region. The location of each such contact is also dictated by two distances, which are shown by way of example with respect to contact C
2
. Specifically, a distance CTE
1
is shown as the contact-to-edge distance with respect to contact C
2
, that is, the distance between contact C
2
and the edge of the active region. Additionally, a distance CTG
1
is shown as the contact-to-gate distance with respect to contact C
2
, that is the distance between contact C
2
and gate G
1
. Having illustrated these two distances, various observations may be made about them as relating to the typical implementation of the distances in the prior art. First, for a given source/drain (e.g., source/drain S/D
1
), the distances are the same for each contact. Thus, by way of example in
FIG. 1
, the same distances CTE
1
and CTG
1
apply to contacts C
1
through C
4
. Second, in many configurations, the distances CTE
1
and CTG
1
apply to all contacts for both source/drains of the transistor. For example, under contemporary designs a typical set of design rule minimum values is CTE
1
=0.05 &mgr;m and CTG
1
=0.095 &mgr;m. Further, from these distances it is noted that
FIG. 1
is not drawn to scale, but it is drawn in a manner to provide a relative basis for comparison to later Figures as will be appreciated below. Alternatively, for transistors not implementing the minimums in the design rules, they may implement a second set of distances with larger values for the contact-to-edge and contact-to-gate distances, along with corresponding larger values for L
g
and W
g
. Still further, note that often the limit for one critical dimension may be dependent on the value of another dimension. For example, the minimum from above of CTG
1
=0.095 &mgr;m may apply where L
g
≦0.4 &mgr;m while for L
g
>0.4 &mgr;m then the minimum value for CTG
1
may be CTG
1
=0.125 &mgr;m. Generally, a transistor constructed according to the minimum dimensions allowed by the design rules consumes a lesser amount of integrated circuit area as compared to a transistor drawn using larger dimensions. Moreover, because minimizing area is often a key design goal, then typically most of the transistors in a circuit are constructed according to the minimum size allowed by the design rules, with the exception of W
g
and L
g
. The dimensions W
g
and L
g
for ea

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