Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C365S189080, C365S229000, C327S534000, C327S537000
Reexamination Certificate
active
10993815
ABSTRACT:
The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
REFERENCES:
patent: 5673219 (1997-09-01), Hashimoto
patent: 5883841 (1999-03-01), Wendell
patent: 6021063 (2000-02-01), Tai
patent: 6040610 (2000-03-01), Noguchi et al.
patent: 6043562 (2000-03-01), Keeth
patent: 6134171 (2000-10-01), Yamagata et al.
patent: 6236617 (2001-05-01), Hsu et al.
patent: 6341087 (2002-01-01), Kunikiyo
patent: 6373321 (2002-04-01), Yamauchi et al.
patent: 6476641 (2002-11-01), Yoshida
patent: 6525984 (2003-02-01), Yamagata et al.
patent: 6611943 (2003-08-01), Shibata et al.
patent: 6700826 (2004-03-01), Ito
patent: 6744301 (2004-06-01), Tschanz et al.
patent: 6759873 (2004-07-01), Kang et al.
patent: 6850103 (2005-02-01), Ikeno et al.
patent: 6850454 (2005-02-01), Kuge et al.
patent: 6873561 (2005-03-01), Ooishi
patent: 6900690 (2005-05-01), Kang et al.
patent: 6982897 (2006-01-01), Luk et al.
patent: 7170327 (2007-01-01), Aksamit
patent: 2005/0128789 (2005-06-01), Houston
patent: 2005/0224799 (2005-10-01), Yamamoto et al.
Tschanz et al., “Dynamic sleep transistor and body bias for active leakage power control of microprocessors”, Nov. 2003, □□Solid-State Circuits, IEEE Journal of, vol. 38, Issue 11, pp. 1838-1845.
Chatterjee Amitava
Houston Theodore W.
Scott David Barry
Tang Shaoping
Wu Zhiqiang
Brady III W. James
Chiang Jack
McLarty Peter K.
Rossoshek Helen
LandOfFree
Design method and system for optimum performance in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Design method and system for optimum performance in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design method and system for optimum performance in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3751202