Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-13
2005-09-13
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06944840
ABSTRACT:
Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.
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Ishii Tatsuki
Matsumoto Itaru
Nagao Yousuke
Sasaki Tetsuo
Dimyan Magid Y.
Hitachi Information Technology Co., Ltd.
Hitachi Software Engineering Co. Ltd.
Mattingly, Stanger, Malur & Brondidge, P.C.
Whitmore Stacy A.
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