Design hierarchy-based placement

Details Design hierarchy-based placement Design hierarchy-based placement

1998-01-09

2001-06-19

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06249902

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrated circuit design, and particularly to a system for determining the physical placement of a hierarchically designed circuit within an integrated circuit.
2. Description of Background Art
A conventional integrated circuit design process includes two major steps: logic design, and physical design. During the logic design step, the design concept is ordinarily described using a hardware description language (HDL) to produce an HDL file. The HDL file is then converted into a netlist format describing set of logic gates, such as AND, OR, etc., and the interconnections between such gates. Many commercially available logic synthesis tools transform HDL files into netlist format.
During the physical design step, the manner in which gates and connections described in the netlist file are to be placed and routed is determined. Various placement algorithms attempt to optimize certain parameters relative to chip die size, wire length, timing, power consumption, or routing congestion. Once placement and routing are determined, mask information is generated for controlling integrated circuit (IC) production.
Before deep submicron circuit processing became available, gate delays dominated signal path delays in ICs. Hence circuit timing could be determined mostly by analyzing netlist gates or logic and it was not necessary to analyze the physical implementation (placement and routing) of the gates, cells, or circuits. Thus logic design and physical design could be effectively decoupled. However, with the advent of deep submicron circuit technology, and significantly shrinking device geometries, circuit timing and design considerations are increasingly dominated by interconnect delays. Given this emerging design paradigm shift, there is a need for providing improved linkage between logic design and physical design.


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