Design for testability in very high speed memory

Details Design for testability in very high speed memory Design for testability in very high speed memory

1999-03-08

2001-05-22

Chung, Phung M. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

06237115

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention is related to testing semiconductor memories and in particular testing very high speed memories.
2. Description of Related Art
The speed of today's computers places demands on the speed of memory chips to keep pace. As the memory chips get faster the ability to test them becomes more difficult and costly to develop new and faster testers. This is compounded by needing to probe the memory chips while still in a wafer form so that they can be sorted for performance. The impedance characteristics of the probes places additional limitations on the ability to test fast memory chips.
In U.S. Pat. No. 5,831,918 (Merritt et al.) an on chip timing circuit has an oscillator which is controlled by a test key that varies the frequency of the oscillator. This test circuit is used in stress testing a DRAM. In U.S. Pat. No. 5,457,400 (Ahmad et al.) an internal test circuit is provided with an additional conductive layer to power the test circuit. The test circuit is used to test DRAM's and other memory devices at the wafer level. In U.S. Pat. No. 4,890,270 (Griffith) a circuit is contained on a chip to determine the speed at which the particular chip operates. An external clock provides a bench mark against which to compare the operations of the chip can be compared.
In order to perform a performance test at the wafer level on high speed memory chips, fast testers and improved probes are required to apply high speed signals and detect the test results. This places a strain on resources to constantly keep up with the evolution of high speed memory chips. A means is needed that allows the memory chips to be tested for functional performance prior to sorting at the wafer level. Being able to do this improves through put, yield and reduces testing at higher package levels.
SUMMARY OF THE INVENTION
In this invention a test circuit is embedded on each memory chip on a wafer to perform performance testing at the wafer level on high performance memory chips. These high performance memory chips have speeds that are faster than the tester performing the tests. The test circuit embedded onto the memory chip provides a means by which a performance test of the high speed chips can be made. A tester clock signal and other memory signals are connected to the memory chip on a wafer through a set of probes. The test circuit receives a sync pulse from the memory chip and transforms the sync pulse into a delay window within which such operations as read and write must perform correctly. If the various memory operations perform within this delay window the memory chip is considered tested good at that particular performance. The delay window is less than a tester clock period and allows high speed memory chips to be tested for performance that is faster than the clock rate of the tester. Although this test circuit was created for wafer level testing it can also be used at higher level of packaging.
An input sync pulse synchronized with the tester clock is connected to the input of the test circuit. The input sync pulse is passed through to the output of the test circuit and at the same time connected to a timer circuit. The timer circuit passes the leading edge of the sync pulse quickly through to the output of the test circuit and delays the lagging edge of the input pulse. A timed delay between pulses is created at the output of the test circuit creating a delay window. This delay window is a result of the combination of the lagging edge of the input sync pulse and the delayed lagging edge of the input sync pulse from the output of timer circuit. The formed delay window is less than a tester clock period and is used to time various operations of the memory chip such as read and write. The amount of the timed delay can be adjusted by adjusting parameters of the timer circuit to provide a maximum permissible delay for the various memory operations. Chips that operate within the maximum permissible delay are tested good. Chips that fail the performance test are often caused by weak bits that degrade the performance and can be repaired to test good. These failures are not identified at wafer test with low frequency testing and by repair and retest can increase the yield at wafer test.
The test circuit and test method discussed herein provides a means to detect performance failures at the wafer level and repair those failures using redundant cells. The repair can allow the memory chip to pass the wafer level performance test by replacing weak cells, and can increase product tested good at the package level. The net result of the performance testing at the wafer level by the test circuit of this invention is that failed product can be repaired at a low level of assembly with fewer bad product passed on to package test, and package level yield can be higher resulting in fewer failures at field test.


REFERENCES:
patent: 4890270 (1989-12-01), Griffith
patent: 5099196 (1992-03-01), Longwell et al.
patent: 5222066 (1993-06-01), Grula et al.
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5831918 (1998-11-01), Merritt et al.

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