Design for high density memory with relaxed metal pitch

Details Design for high density memory with relaxed metal pitch Design for high density memory with relaxed metal pitch

1999-05-17

2000-05-02

Tsai, Jey

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257390, 257758, H01L 218242

Patent

active

060575735

ABSTRACT:
A method and design for stitching polysilicon wordlines to straps formed of interconnected metal line segments formed in two or more metallization levels. Each strap comprises a continuous conductive metal line passing alternatively from one metal layer to another in a selected sequence. The sequence of segments in each strap alternates in phase with the sequence in next nearest neighbor straps but may be in phase with second nearest neighbor straps. Thereby the pitch of strap segments on each metallization level is at least twice that of the subjacent polysilicon wordlines. The total length of each metal in each strap is the same in all straps. This arrangement allows the use of metals having different resistivities in each strap with all the straps having identical overall resistance. The metals used in the two or more levels may also have different minimum design rules without compromising the identical overall performance of all the straps. In a second embodiment a method and design is described for doubling the length of polysilicon sub-wordlines in a sub-wordline memory array without reducing performance by connecting sub-wordline to sub-wordline decoders by metal straps connected to the sub-wordlines midpoints.

REFERENCES:
patent: 5990507 (2000-01-01), Mochizuki et al.
patent: 6018195 (2000-01-01), Takebuchi

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