Design flow method for integrated circuits

Details Design flow method for integrated circuits Design flow method for integrated circuits

2006-02-28

2006-02-28

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07007263

ABSTRACT:
The design flow method of the present invention accurately performs timing analysis during the circuit design stage, so that the DFT synthesis procedure can effectively control the timing information, preventing timing violation from happening during the IC design flow process. Furthermore, the information of the CTS procedure and the static-timing analysis procedure is combined to perform accurate timing estimation.

REFERENCES:
patent: 6377912 (2002-04-01), Sample et al.
patent: 6769107 (2004-07-01), Watkins

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