Design circuit pattern for test of semiconductor circuit

Details Design circuit pattern for test of semiconductor circuit Design circuit pattern for test of semiconductor circuit

2001-09-24

2004-02-17

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06694500

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit pattern designed for test of a semiconductor circuit in which each of a plurality of circuits formed on a semiconductor wafer according to individual design conditions are the object of electrical measurement and evaluation.
In particular, the present invention relates to the technique of evaluation of the production of semiconductor used when a difference between a design pattern and a circuit pattern formed on a wafer comes out according to design condition so that the correction or reformation of design pattern designed for the production of semiconductor is needed.
2. Description of the Related Art
In recent years, higher integration and function were being requested for various LSI (large scale integrated circuits) typified by ASIC (application specific integrated circuits) from the tendency for the electrical device to be made highly functional, lightweight, thin, short and small. Namely, it is desired to make chip size as small as possible to realize high function for LSI such as ASIC.
The above-mentioned LSI such as ASIC is formed through several steps for the production of semiconductor device of forming figure data which is also called “pattern data” for the production of photomask pattern through functional design, logic design, circuit design and layout design, forming photomask using the figure data and thereafter transferring pattern of the photomask onto a wafer by demagnification projection.
Photomask is generally formed using the above-mentioned figure data (pattern data) and through steps of writing the figure data on photosensitive resist put on the shading film of photomask substrate (it is also called “photomask blanks”) by means of electron beam exposure system or aligner of photo such as excimer wavelength, developing and etching.
Namely, photomask having a desired metallic thin film pattern can be obtained through the following steps of: applying photosensitive resist on a photomask substrate provided with a shading metallic thin film on a one face of a glass substrate, and drying the photosensitive resist; applying ionizing radiation only to the given area by means of aligner to form a latent image; developing the photosensitive resist with latent image to obtain a resist pattern with a desired shape corresponding to the area to which ionizing radiation is applied; and working the metallic film into the shape of resist pattern using the resist pattern as etching-proof resist by etching.
In this case, when a pattern of photomask is transferred to a wafer by demagnification projection, the photomask is also called “reticle mask”.
In such a manner, a circuit pattern is formed on a wafer by transferring a pattern of photomask on a wafer by demagnification projection. However, electrical property of the circuit pattern formed on a wafer is not always determined by only the two-dimensional shape of circuit pattern, but by the three-dimensional shape of circuit pattern. Therefore, it has been carried out to form a test circuit pattern for evaluation on a wafer and evaluate the electrical property of the test circuit pattern.
Further, in a former case which can be based on the assumption that the formed circuit pattern of LSI is not made so small that a test design pattern of photomask is faithfully formed on a wafer, a scale of a test circuit pattern is small, in which the number of test cells used for the object of the specific evaluation was within several tens.
However, recently, a size of the pattern exposed (a size of the pattern exposed on a wafer) was made finer as the integration of LSI is made higher and higher so that a size of the pattern exposed approached the wavelength of rays or became smaller than the wavelength of rays exposed. Therefore, a deformation of the exposed shape called “optical proximity effect” came to arise when a pattern of photomask is transferred on a wafer through demagnification projection. As a result, there was a case where a pattern was not formed on a wafer with the same size as another pattern according to design conditions, even if the pattern is a pattern having the same size as another pattern on photomask. This influences the electrical property of circuit formed on a wafer. Accordingly, the necessity appeared that test circuit patterns must be formed both on a wafer and on a photomask, according to design conditions.
The test circuit patterns enables to appropriately correct a pattern on a photomask or to appropriately reform a design pattern on a photomask.
Further, referring to the drawings, the necessity of a circuit pattern designed for test on a wafer (hereafter, it is called “test design circuit”) is explained concretely.
As shown in FIG.
7
(
a
), in the design of semiconductor circuit, two-dimensional design pattern
201
is formed, wherein as shown in FIG.
7
(
b
), a circuit pattern formed on a semiconductor wafer becomes a figure pattern (it is called “circuit pattern”)
202
having the sectional shape different from the design pattern (a).
A section taken on line D
1
-D
2
of design pattern
202
formed on a wafer shown in FIG.
7
(
b
) has the shape of section shown for example indicated by numeral
204
shown in FIG.
7
(
c
).
In order to determine the electrical property of a pattern formed on a semiconductor wafer according to the three-dimensional shape thereof, it is necessary to design a test design pattern
210
as shown in
FIG. 8
as the shape of pattern on a photomask and to form a pattern on a semiconductor wafer wherein the electrical property of the pattern formed on a semiconductor wafer is evaluated.
In
FIG. 8
, numeral
211
designates a circuit portion of the object of evaluation and numeral
212
designates a wiring portion.
Further, in
FIG. 8
, numeral
213
and
214
designates pads, which are connection portions between a semiconductor wafer and an electrical measuring instrument, in which pads necessitate a least areas of 80 &mgr;m square on a semiconductor wafer for physical contact of the pads with a needle.
Pads
213
,
214
are connected with circuit portion
211
wherein the object of evaluation of test pattern
210
through wiring portions
212
which are wirings with secure thickness for the electrical connection to the circuit portion
211
.
Design rule of semiconductor circuit is determined by evaluating the electrical property of a pattern on a semiconductor wafer by the test design circuit pattern, by which design based on the two-dimensional information is made possible.
However, from the latter half of the 1990s, the meaning of “test design circuit pattern” begins to change, as the technique for forming a pattern with a size smaller than the wavelength of rays from semiconductor exposure is extensively carried out.
FIG.
9
(
a
) shows design patterns including figures with the size smaller than the wavelength of rays from a semiconductor exposurer or exposure device. FIG.
9
(
b
) shows an example of a pattern formed on a semiconductor wafer by projecting the design pattern onto a semiconductor wafer by demagnification projection.
This is called optical proximity effect wherein a pattern cannot be formed on a semiconductor wafer as the design pattern.
In FIG.
9
(
a
) numerals
221
,
222
and
223
designate design patterns. In FIG.
9
(
b
), numerals
224
,
225
and
226
designate patterns on a wafer corresponding to design patterns
221
,
222
and
223
, respectively.
FIG.
10
(
a
) shows patterns provided with correction patterns at corners thereof so as to reduce deformations caused by optical proximity effect. FIG.
10
(
b
) shows patterns with the shape being near to the objective shape of pattern formed by projecting the design patterns shown in FIG.
10
(
a
) onto a semiconductor wafer by demagnification projection, which is called “optical proximity effect correction technique”.
In FIG.
10
(
a
), numerals
241
,
242
and
243
designate design patterns. In FIG.
10
(
b
), numerals
244
,
245
and
246
designate patterns formed on a wafer corresponding t

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