Design-based monitoring

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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C438S010000, C438S017000

Reexamination Certificate

active

07135344

ABSTRACT:
A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.

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patent: 6529621 (2003-03-01), Alles et al.
patent: 2003/0229881 (2003-12-01), White et al.
patent: 2005/0004774 (2005-01-01), Volk et al.
Applied Materials Israel, Ltd., International Search Report and Written Opinion, PCT/US2004/02229, Oct. 14, 2004, 9 pp.
Sebasta W W et al, Development of a New Standard for Test, Sep. 10, 1999, Proceedings of the International Test Conference, Washington, pp. 988-993.

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