Design and process for a dual gate structure

Details Design and process for a dual gate structure Design and process for a dual gate structure

1999-10-25

2002-07-02

Nguyen, Viet Q. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S283000

Reexamination Certificate

active

06413803

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a dual gate structure, for a metal oxide semiconductor field effect transistor, (MOSFET), device, featuring a metal plug structure, formed at the N doped, and P doped regions, of a polysilicon dual gate structure.
(2) Description of Prior Art
To satisfy the low voltage, and low threshold voltage requirements, needed to reduce power consumption, and increase performance for ultra large scale integrated, (ULSI), devices, the semiconductor industry is using surface channel MOSFET devices, in place of buried channel counterparts. The polysilicon dual gate structure, used for both N channel, (NMOS), surface channel devices, and for P channel, (PMOS), surface channel devices, is comprised with N type doping, in the region of the dual gate structure which traverses the NMOS devices, and is comprised with P type doping, in regions in which the same dual gate structure traverses the PMOS devices. This dopant configuration, for the polysiicon dual gate structure, can however present a performance degrading, diode effect, at the interface between dopant regions in the polysilicon dual gate structure.
This invention will describe the use of a metal plug structure, formed overlying and contacting the region of the polysilicon dual gate structure, in which the dopant interface resides, alleviating the diode effect at the dopant interface by allowing the current flow, in the polysilicon dual gate structure, to pass through the less resistive metal plug structure. This invention will offer two process iterations, for forming the metal plug structure, in addition to describing the design of the dual gate structure, comprised with the metal plug structure. Prior art such as Lee et al, in U.S. Pat. No. 5,900,658, describe a process for forming both logic and memory MOSFET devices, on the same semiconductor chip, however that prior art does not describe the novel process and design, for fabricating a metal plug structure, to alleviate the diode effect, at the dopant interface, of a dual gate structure.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a semiconductor device comprised with NMOS surface channel devices, and with PMOS surface channel devices.
It is another object of this invention to use a polysilicon dual gate structure, comprised with N type doping in the NMOS region of the semiconductor device, and comprised with P type doping in the PMOS region of the semiconductor device.
It is still another object of this invention to form a metal plug structure, to contact the portion of the polysilicon dual gate structure, in which the dopant interface exists.
It is still yet another object of this invention to form the metal plug structure on a metal silicide layer, in a region in which the metal silicide layer overlays the dopant interface, or to form the metal plug structure, directly on the dopant interface, in the polysilicon dual gate structure, with the metal plug structure located in an opening formed using self-aligned contact procedures.
In accordance with the present invention a process for forming a metal plug, on a polysilicon dual gate structure, with the metal plug located on the dopant interface of the polysilicon dual gate structure, is described. A first iteration of this invention entails forming the metal plug structure, on a metal silicide layer, in a region in which the metal silicide layer overlays the dopant interface, in the polysilicon dual gate structure. After formation of an undoped, polysilicon dual gate structure, on an underlying gate insulator layer, a first photoresist shape is used to block out PMOS regions, allowing a first ion implantation procedure to form a N type, lightly doped source/drain region, in an NMOS region. A second photoresist shape is then employed to block out NMOS regions from a second ion implantation procedure, used to form a P type, lightly doped source/drain region, in PMOS regions. After formation of insulator spacers, on the sides of the polysilicon dual gate structure, a third photoresist shape is used to block out PMOS regions from a third ion implantation procedure, used to create an N type, heavily doped source/drain, in the NMOS region, in addition to forming a N type region, in the portion of the polysilicon dual gate structure, located in the NMOS region. A fourth photoresist shape is next used to block out the NMOS regions, allowing a fourth ion implantation procedure to create a P type, heavily doped source/drain region, in the PMOS region, as well as creating a P type region, in the portion of the polysilicon dual gate structure, residing in the PMOS region. After formation of a metal silicide layer, on the top surface of all heavily doped source/drain regions, as well as on the top surface of the polysilicon dual gate structure, an interlevel dielectric, (ILD), layer is deposited, and planarized. Conventional photolithographic and reactive ion etching, (RED), procedures are used to create openings in the ILD layer, exposing portions of the metal silicide layer: directly overlying: the N type region, and the P type region of the polysilicon dual gate structure; directly overlying the N type, and P type, heavily doped source/drain regions; and directly overlying the dopant interface in the polysilicon dual gate structure. Metal plug structures are next formed in all openings, followed by the formation of metal interconnect structures, overlying and contacting all metal plug structures, except the metal plug structure, that overlaysthe dopant interface of the polysilicon dual gate structure.
A second iteration of this invention entails initially creating the N type, and P type regions, in a polysilicon layer, followed by the deposition of a first silicon nitride layer. After definition of a silicon nitride capped, polysilicon dual gate structure, the sequence of photoresist block out masks, and ion implantation procedures, and insulator spacer formation, used with the first iteration, are again used to create the N type, lightly doped, and N type, heavily doped source/drain regions, in the NMOS region, while P type, lightly doped, and P type heavily doped source/drain regions, are created in the PMOS regions. A second silicon nitride layer is next deposited, followed by the creation of openings in the silicon nitride layers, exposing regions of the polysilicon dual gate structure to be subsequently overlaid by metal plug structures. After deposition and planarization of an ELD layer, borderless, or self-aligned openings, are created in the ILD layer, aligned with the openings in the silicon nitride layer, exposing a portion of the top surface of the N type region, and the P type region, in the polysilicon dual gate structure; the heavily doped source/drain regions; and of the dopant interface in the polysilicon dual gate structure. Metal plug structures are next formed in the self aligned openings, followed by the creation of metal interconnect structures, overlying, and contacting, all metal plug structures, except the metal plug structure, located on the dopant interface of the polysilicon dual gate structure.


REFERENCES:
patent: 5668024 (1997-09-01), Tsai et al.
patent: 5674775 (1997-10-01), Ho et al.
patent: 5677249 (1997-10-01), Fukui et al.
patent: 5900658 (1999-05-01), Lee et al.
patent: 6174775 (2001-01-01), Liaw
patent: 6207482 (2001-03-01), Shih et al.

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