Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-16
2005-08-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06931612
ABSTRACT:
A method for optimizing an algorithm specified for implementation on an integrated circuit for a specified application. The algorithm is analyzed with respect to its performance, and estimates of implementation area and speed are calculated. Specifically, the degrees of freedom for the algorithm alternations under specific targeted implementation objective functions and constraints are identified. The algorithm solution space is then searched to identify the algorithm structure that is best suited for the specified design goals and constraints. Algorithm parameters which satisfy performance metrics and can be implemented with minimum silicon area are identified.
REFERENCES:
patent: 5031111 (1991-07-01), Chao et al.
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5537341 (1996-07-01), Rose et al.
patent: 5572436 (1996-11-01), Dangelo et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5845233 (1998-12-01), Fishburn
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5966534 (1999-10-01), Cooke et al.
patent: 6051031 (2000-04-01), Shubat et al.
patent: 6099577 (2000-08-01), Isobe
patent: 6260185 (2001-07-01), Sasaki et al.
patent: 6269277 (2001-07-01), Hershenson et al.
patent: 6334202 (2001-12-01), Pielmeier
patent: 6539536 (2003-03-01), Singh et al.
patent: 6691301 (2004-02-01), Bowen
patent: 6701501 (2004-03-01), Waters et al.
patent: 6735744 (2004-05-01), Raghunathan et al.
patent: 6760888 (2004-07-01), Killian et al.
patent: 2002/0133788 (2002-09-01), Waters et al.
patent: 2003/0014743 (2003-01-01), Cooke et al.
patent: 2003/0208723 (2003-11-01), Killian et al.
patent: 2004/0143801 (2004-07-01), Waters et al.
patent: 06176009 (1994-06-01), None
patent: WO 200072096 (2000-11-01), None
Meguerdichian et al., “MetaCores: Design and Optimization Techniques”, Design Automation Conference, Jun. 18, 2001, pp. 585-590.
Lee et al., “On the design automation of the memory-based VLSI architectures for FIR filters”, IEEE Transactions on Consume Electronics, vol. 39, No. 3, Aug. 1993, pp. 619-629.
Wu et al., “Register minimization beyond sharing among variables”, IEEE Transactions on Computer-Aided Design of Integrate Circuits and Systems, vol. 15, No. 12, Dec. 1996, pp. 1583-1587.
NN84024652, “Area Minimization Under Geometric Constraints”, IBM Technical Disclosure Bulletin, vol. 26, No. 9, Feb. 1984, pp. 4652-4653 (3 pages).
NN9308589, “Recursive Binary Partitioning Algorithm for Database Access Skew Characterization”, IBM Technical Disclosure Bulletin, vol. 36, No. 8, Aug. 1993, pp. 589-594 (7 pages).
Joeresson et al., “Soft-output viterbi decoding: VLSI implementation issues”, IEEE 43rd Vehicular Technology Conference, May 18, 1993, pp. 941-944.
Lu et al., “Technology mapping for minimizing gate and routing area”, Proceedings of Design, Automation and Test In Europe, Feb. 23, 1998, pp. 664-669.
Megerian Seapahn
Mogre Advait
Petronavic Dusan
Potkonjak Miodrag
Conley & Rose, P.C.
Kik Phallaka
LSI Logic Corporation
Smith Matthew
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