Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-03-31
2000-05-23
An, Meng-Ai T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
712 28, 712236, 714 2, 714 8, 714 10, 714 11, 714 13, 714 25, 714 31, 714 40, 714 41, 714710, G06F 1122
Patent
active
060676337
ABSTRACT:
A multi-processor system and methodology optimize overhead costs associated with manufacturing large integrated circuit devices having multiple data processors and processing elements thereon by effectively disabling processing elements that are not functional. Disabling the processing elements is performed through segmented power distribution on an integrated circuit first-level package or by providing inhibit signals in pre-selected logic states based on the functionality of the multi-processing system. The functionality of the multiprocessing system is determined during an initial testing procedure, including wafer-level testing.
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Bearden David Ray
Robbins Gordon J.
An Meng-Ai T.
El-Hady Nabil
England Anthony V. S.
International Business Machines Corp
Motorola Inc.
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