Design and fabrication of semiconductor structure having complem

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257369, 257403, 257412, 257616, H01L 2976, H01L 2994, H01L 31062, H01L 31119

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active

059527013

ABSTRACT:
A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

REFERENCES:
patent: 4984043 (1991-01-01), Vinal
patent: 4990974 (1991-02-01), Vinal
patent: 5194923 (1993-03-01), Vinal
patent: 5250818 (1993-10-01), Saraswat et al.
patent: 5619057 (1997-04-01), Komatsu
Bohr et al, "A High Performance 0.35 .mu.m Logic Technology for 3.3V and 2.5V Operation", IEDM Tech. Dig., 1994, pp. 273-276.
Chang et al, "A High-Performance 0.25-.mu.m CMOS Technology: I--Design and Characterization", IEEE Trans. Electron Devices, vol. 39, No. 4, Apr. 1992, pp. 959-966.
Chen, CMOS Devices and Technology for VLSI (Prentice Hall), 1990, pp. 27-33.
Davari et al, "A High-Performance 0.25-.mu.m CMOS Technology: II--Technology," IEEE Trans. Electron Devices, vol. 39, No. 4, Apr. 1992, pp. 967-975.
Grove, Physics and Technology of Semiconductor Devices (John Wiley & Sons), 1967, pp. xiii-xix.
Hanson et al, "Analysis of the Controllability of a Sub-Micron CMOS Process Using TCAD", Proc. International Symposium on Semiconductor Manufacturing, paper IV-3, 1994, 5 pages.
Hillenius et al, "Gate Material Work Function Consideration For 0.5 .mu.m CMOS", Procs. Intl. Conf. Computer Design, 1985, pp. 147-150.
Hu et al, "Design and Fabrication of P-channel FET for 1-.mu.m CMOS Technology", IEDM Tech. Dig., 1982, pp. 710-713.
King et al, "A Polycrystalline-Si.sub.1-x Ge.sub.x -Gate CMOS Technology", IEDM Tech. Dig., 1990, pp. 253-256.
Mead et al, Introduction to VLSI Systems (Addison-Wesley), 1980, pp. 1-37.
Merckel, "Ion Implanted MOS Transistors--Depletion Mode Devices", Process and Device Modeling for IC Design, 1977, pp. 677-688.
Montree et al, "Comparison of buried and surface channel PMOS devices for low voltage 0.5 .mu.m CMOS", Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, 1993, pp. 11-14.
Muller et al, Device Electronics for Integrated Circuits, (Wiley, 2d ed.), 1986, pp. 443-457.
Nakahara et al, "Relief of Hot Carrier Constraint on Submicron CMOS Devices by Use of a Buried Channel Structure," IEDM Tech. Dig., 1985, pp. 238-241.
Nishiuchi et al, "A Normally-off Type Buried Channel MOSFET for VLSI Circuits," IEDM Tech. Dig., 1978, pp. 26-29.
Ng, Complete Guide to Semiconductor Devices (McGraw-Hill), 1995, pp. 163-178.
Nguyen et al, "A Comparison of Buried Channel and Surface Channel MOSFETs for VLSI", IEEE Trans, Electron Devices, vol. ED-29, No. 10, Oct. 1982, pp. 1663-1664.
Ogura et al, "Design and Characteristics of the Lightly Doped Drain--Source (LDD) Insulated Gate Field-Effect Transistor", IEEE Trans. Electron Devices, vol. ED-27, No. 8, Aug. 1980, pp. 1359-1367.
Parrillo et al, "A Fine-Line CMOS Technology that Uses P.sup.+ -Polysilicon/Silicide Gates for NMOS and PMOS Devices", IEDM Tech. Dig, 1984, pp. 418-422.
Rhoderick et al, Metal-Semiconductor Contacts (Oxford University Press), 1988, pp. 11-15, 47, and- 48.
Sze, Physics of Semiconductor Devices (Wiley & Sons, 2d ed.), 1981, pp. 464-469.
Yao et al, "Structure and Frequency Dependence of Hot-Carrier-Induced Degradation in CMOS VLSI," IEEE/Int'l. Reliability Physics Symp., 1987, pp. 195-200.

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