Design and a novel process for formation of DRAM bit line and ca

Details Design and a novel process for formation of DRAM bit line and ca Design and a novel process for formation of DRAM bit line and ca

1999-11-18

2000-10-17

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257303, 257306, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

061335991

ABSTRACT:
A process for fabricating a DRAM cell has been developed, in which two interlaced patterns, each comprised of capacitor node contact holes and bit line contact holes, are independently created, each using a specific photolithographic mask, and a specific photolithographic procedure. The two interlaced patterns allow the creation of the capacitor node contact images, and the bit line contact holes images, to be formed in a thin polysilicon layer, with minimum spacing between contact images. Capacitor node contact holes, as well as bit line contact holes, are than formed in an insulator layer, via a dry etching procedure, using the patterned thin polysilicon layer as a mask. The use of specific masks, or of the interlaced pattern, allows the minimum spacing, between a capacitor node contact hole, and a bit line contact hole, to be limited only by the overlay between photolithographic masks.

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