Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-15
2008-04-15
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11007705
ABSTRACT:
A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.
REFERENCES:
patent: 5638381 (1997-06-01), Cho et al.
patent: 6408424 (2002-06-01), Mukherjee et al.
patent: 6457162 (2002-09-01), Stanion
patent: 2002/0144215 (2002-10-01), Hoskote et al.
patent: 2003/0154485 (2003-08-01), Johnson et al.
patent: 2004/0083443 (2004-04-01), Ogawa et al.
Demos Anastasakis, et al., “A Practical and Efficient Method for Compare-Point Matching,” DAC 2002, Jun. 10-14, 2002.
Mukul R. Prasad, et al., “Solving the Latch Mapping Problem in an Industrial Setting,” DAC 2003, Jun. 2-6, Anaheim, CA (pp. 442-446).
Burch, Jerry R. and Singhal, Vigyan; “Robust Latch Mapping for Combinational Equivalence Checking”; Cadence Berkeley Labs; 1998; 7 pages.
van Eijk, C.A.J.; “Sequential Equivalence Checking Without State Space Traversal”; Design Automation Section, Eindhoven Unvi. of Tech., The Netherlands; Feb. 1998; 6 pages.
Abadir Magdy S.
Anand Himyanshu
Bhadra Jayanta
Chiang Jack
Fortkort John A.
Fortkort & Houston P.C.
Freescale Semiconductor Inc.
Memula Suresh
LandOfFree
Design analysis tool and method for deriving correspondence... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Design analysis tool and method for deriving correspondence..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design analysis tool and method for deriving correspondence... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3943145