Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-15
2008-04-15
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07360183
ABSTRACT:
A method and system automatically generates a bit-cell correspondence between a first memory model and a second memory model of a memory. The method includes receiving data from the first and the second memory model, obtaining true-inverted fan-in cones for words in the memory models to obtain correspondence between sets of words in the two models, writing word binary sequences into the words to obtain a set of bit-cell correspondences, and using inherent structural information in memory designs to generalize bit-cell correspondence obtained on bit-cells of a pair of corresponding words to obtain bit-cell correspondence information for all the bit-cells in the memory models. Correspondence is detected if one of the bit-cell binary sequences written into a bit-cell in the first memory model is equal to or an invert of another of the bit-cell binary sequences written into a bit-cell in the second memory model.
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Abadir Magdy S.
Anand Himyanshu
Bhadra Jayanta
Chiang Jack
Fortkort John A.
Fortkort & Houston P.C.
Freescale Semiconductor Inc.
Memula Suresh
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