Descriptor-based load balancing

Details Descriptor-based load balancing Descriptor-based load balancing

2005-12-27

2005-12-27

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Transfer termination

C710S001000, C710S020000, C710S021000, C710S022000, C710S035000, C710S308000, C710S033000, C718S100000, C718S101000, C718S105000, C709S201000, C709S212000, C709S213000, C709S238000, C709S250000, C712S028000, C712S029000, C712S030000, C712S032000, C370S351000, C370S352000, C370S218000

Reexamination Certificate

active

06981074

ABSTRACT:
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

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