Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-02
2008-12-30
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07472371
ABSTRACT:
A logic circuit described in the netlist style HDL and a lower-level logic circuit (lower-level module) of a library which corresponds to an instance in the logic circuit and is described in the RTL style are read to a logic circuit storage unit by a logic circuit reading unit. A library hierarchical expansion unit performs a process of expanding a hierarchy of the library with respect to the instance in the logic circuit and converts it to the RTL style. An assignment statement eliminating unit replaces and eliminates an assignment statement in the logic circuit, which is converted to the RTL style. A logic circuit output unit outputs the logic circuit, which has undergone the conversion, in the RTL style. If the logic circuit of the library is described in the netlist style HDL, it is converted to an RTL style HDL as well as the case of the logic circuit.
REFERENCES:
patent: 5867395 (1999-02-01), Watkins et al.
patent: 2007/0174805 (2007-07-01), Hsu et al.
patent: 9-311882 (1997-12-01), None
patent: 11-85832 (1999-03-01), None
patent: 2004-287669 (2004-10-01), None
Fujitsu Limited
Garbowski Leigh Marie
Staas & Halsey , LLP
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