Depth buffer for rasterization pipeline

Details Depth buffer for rasterization pipeline Depth buffer for rasterization pipeline

2004-11-04

2011-12-20

Washburn, Daniel (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics processing

Three-dimension

C345S421000, C711S167000, C365S189011

Reexamination Certificate

active

08081182

ABSTRACT:
By locating the depth buffer of a 3D graphics rasterization pipeline in a dedicated high speed memory, bandwidth on a main bus can be eliminated that would otherwise result from hidden surface removal (HSR) hardware contained in the pipeline. Also, by reordering of read and write access commands to the depth buffer memory, it is possible to improve memory access throughput otherwise impacted by an increased latency of a read access.

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