Deposition process for forming void-free dielectric layer

Details Deposition process for forming void-free dielectric layer Deposition process for forming void-free dielectric layer

1999-07-13

2001-05-22

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S788000, C427S569000, C427S579000, C427S585000

Reexamination Certificate

active

06235647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for forming a void-free dielectric layer.
2. Description of Related Art
FIG. 1
is a schematic, cross-sectional view of a conventional deposition process. As shown in
FIG. 1
, a substrate
100
and a metal pattern
102
over the substrate
100
are provided, and they are covered with a high density plasma (HDP) dielectric layer
104
. The HDP dielectric layer
104
often has several sharp corners
105
on its surface over the metal pattern
102
.
Still referring to
FIG. 1
, a deposition layer
106
is formed over the HDP dielectric layer
104
. The deposition layer
106
is conventionally made of a low-cost material, such as a silane-based (SiH
4
-based) material. However, the SiH
4
-based material has poor step coverage on the sharp corners
105
, and therefore has voids
120
therein after it is deposited over the HDP dielectric layer
104
. The voids
120
are easily exposed and filled with polishing slurry in the following chemical-mechanical polishing step. This polishing slurry in the voids affects the electricity, yield and reliability of the deposition layer
106
.
Moreover, in the following via process, the voids
120
are defect sources on the vertical sidewall of the via hole. Those defects on the sidewalls often induce ‘volcanoes’ when a tungsten plug is formed on a barrier layer over the via hole. The volcanoes, which are rapid reactions between the titanium (Ti) barrier layer and tungsten fluoride (WF
6
, a tungsten plug material source), often cause via hole failures in the via process.
Although forming the deposition layer from a material with good step coverage inhibits void formation, it costs much more than forming the deposition layer from a SiH
4
-based material.
Forming the deposition layer by high density plasma (HDP) deposition also inhibits void formation. However, the HDP deposition is a high-cost technique, and is also a technique that easily charge damages the underlying features on the substrate.
SUMMARY OF THE INVENTION
The invention provides a deposition process. The process comprises high-density-plasma depositing a first dielectric layer on a conductor pattern, depositing a second dielectric layer conformal to the first conductor layer, and depositing a third dielectric layer on the second dielectric layer. In this process, the first, second, and third dielectric layers can be formed by high density plasma deposition, atmospheric pressure deposition, and plasma enhanced deposition, respectively. The second dielectric layer can be alternatively formed by plasma enhanced deposition.
Moreover, the second dielectric layer is preferably made of a tetraethosiloxane-based (TEOS-based) material, and is preferably formed to a thickness of about 500 angstroms to about 2000 angstroms.
The conformal second dielectric layer moderates the sharp topograph of the first dielectric layer formed by HDPCVD, and thus inhibits void formation when depositing the third dielectric layer thereon. Without voids, problems stemming from the voids such as slurry effects or via hole failures are solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5968610 (1999-10-01), Liu et al.
patent: 6077784 (2000-06-01), Wu et al.

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