Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-18
2002-04-30
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S631000, C438S633000, C438S669000, C438S692000
Reexamination Certificate
active
06380074
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method preferably for shrink-hole-free filling of trenches in integrated semiconductor circuits by utilizing selective growth of a layer to be applied. In which a layer of a selectively growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer, wherein largely flattened raised portions which, before the layer of the selectively growing material is applied, are covered by the growth-inhibiting layer at least on their sides.
Such a method is known from Published, Non-Prosecuted German Patent Application DE 196 31 743 A1. In this document, a method is described in which a first insulating layer is applied to a semiconductor substrate and a metal layer is deposited thereupon and patterned so that raised portions in the form of conductor tracks are produced on the first insulation layer. This pattern is covered with a second insulation layer that is then removed on the bottom of the trenches located between the raised portions or conductor tracks, respectively. As a result, the first insulation layer is exposed at the bottom of the trenches. The pattern produced is, therefore, covered in places by the first insulation layer and in places by the second insulation layer. Onto this pattern, a layer of a selectively growing material is applied. When the layer of the selectively growing material is being applied, the first and second insulation layer are growth-promoting and growth-inhibiting, respectively, in the sense that the growth rate of the layer of selectively growing material to be applied is greater over the first insulation layer than over the second one.
If the second insulation layer is to be removed at the bottom of the trenches but not at the top of the raised portions, a resist mask must be applied and patterned in such a manner that the raised portions are covered by the mask whereas the trenches are exposed. This requires a corresponding additional effort in the production of integrated circuits. If this effort is avoided and, instead, the bottom of the trenches without masking is exposed with the aid of anisotropic etching, the second, growth-inhibiting layer is also removed from the top of the raised portions. When the selectively growing layer is then applied, the growth rate there is greater than desired. Another application of the growth-inhibiting material to the surface of the raised portions would again entail corresponding additional effort. The additional effort arising in both cases is due to the fact that the growth-inhibiting layer is removed exclusively at the bottom of the trenches, i.e. precisely where it is most inaccessible.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a deposition of various base layers for selective layer growth in semiconductor production which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for shrink-hole-free filling of a trench. The method includes the step of providing a semiconductor substrate having raised portions with flattened top surfaces and trenches with bottom surfaces formed therein, the flattened top surfaces of the raised portions and the bottom surfaces of the trenches being formed substantially parallel to the semiconductor substrate. At least sides of the raised portions are covered with a growth-inhibiting layer. A growth-promoting layer is formed by anisotropic treatment on surfaces parallel to the substrate including the flattened top surfaces of the raised portions and the bottom surfaces of the trenches. The growth-promoting layer is removed from the flattened top surfaces of the raised portions. A layer of a selective growing material is applied simultaneously to the growth-promoting layer and to the growth-inhibiting layer.
In the method according to the invention, a pattern is provided with raised portions and is prepared in the simplest possible manner for the application of a layer of a selective growing material. The pattern is intended to exhibit a growth-inhibiting layer on the top and the side walls of raised portions and a growth-promoting layer at the bottom of trenches between the raised portions. It should be possible to produce this pattern in as time-saving and cost-saving a manner as possible.
According to the invention, the object is achieved by the fact that, after the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on the surfaces on the raised portions which are parallel to the substrate. According to the invention, the sequence of application of the growth-promoting layer and the growth-inhibiting layer is reversed. First, the growth-inhibiting layer is applied and only then the growth-promoting layer is generated perpendicularly to the surface of the semiconductor substrate at the bottom of the trenches and on the top of the raised portions with the aid of anisotropic treatment. Due to this sequence, it is the growth-promoting layer that is located at the bottom of the trenches after the deposition of both layers and, therefore, no further processing is required there. The growth-promoting layer, which has also been generated on the top of the raised portions by dispensing with masking can now be removed much more easily than in the previously known method at the bottom of the trenches.
A preferred embodiment provides that the growth-promoting layer is removed by chemical/mechanical polishing on the surfaces parallel to the substrate on the raised portions. The polishing process can be very brief, depending on the deposited thickness of the growth-promoting layer.
A further development of the invention provides that the growth-inhibiting layer is converted on the surface into the growth-promoting layer on the surfaces parallel to the substrate. This can be done, for example, with the aid of an oxygen plasma or by low-energy implantation of oxygen into the growth-inhibiting layer.
With regard to the materials used, preferred embodiments provide that the growth-promoting layer consists predominantly of silicon or silicon oxide and the growth-inhibiting layer consists predominantly of silicon nitride, the silicon nitride preferably being converted into silicon oxide by the implantation of oxygen.
The raised portions are typically conductive patterns of a metalization layer, in which case the selectively growing material forms an insulation between successive metal layers. However, the raised portions can also be conductive gate patterns on which a first oxide layer is applied below the metalization.
The selective growing material is preferably deposited out of an atmosphere containing ozone and TEOS (tetraethyleneorthosilicate) and silicate glass doped with boron and phosphorus.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a deposition of various base layers for selective layer growth in semiconductor production, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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patent: 6008107 (1999-12-01), Pierce et al.
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Gabric Zvonimir
Glawischnig Hans
Kirchhoff Markus
Schilling Uwe
Sperlich Hans-Peter
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Thanh
Stemer Werner H.
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