Deposited tunneling oxide

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reissue Patent

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C257S320000, C257S317000

Reissue Patent

active

RE038370

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of integrated circuit processing and more specifically to a method of depositing tunneling oxide in an electrically erasable read-only memory device.
BACKGROUND OF THE INVENTION
EEPROM devices are nonvolatile memory devices in which the presence or absence of charge on a floating gate electrode indicates a binary one or zero. One EEPROM device is described in U.S. Pat. No. 4,579,706, entitled “Nonvolatile Electrically Alterable Memory”. This patent is herein incorporated by reference. In this type of EEPROM device, the floating gate electrode is electrically insulated from the other electrodes of the device by one or more layers of tunneling oxide. Electrical charge is transferred to the floating gate by placing a voltage on a programming electrode which is sufficient to cause electrons to tunnel through the tunneling oxide to the floating gate electrode. In EEPROM devices, the tunneling oxide can conduct only a limited amount of charge under the high fields imposed across the oxide during tunneling before the tunneling oxide fails or breaks down, thus limiting the number of programming cycles. In some tunneling elements in an EEPROM array, this failure may occur in less than approximately 10,000 programming cycles, depending on the uniformity and intrinsic defect density of the tunneling oxide layer or layers.
The characteristics of the tunneling oxide layer are critical to the life and operation of an EEPROM device. In prior EEPROM devices, tunneling oxides are produced by growing an oxide using a thermal oxidation process. However, with this type of process, the oxide defect density is quite high, which causes a large number of early breakdown failures. As presently understood, this is because any defects in the underlying silicon may propagate into the silicon dioxide layer as it is grown. Furthermore, during the thermal oxidation process, the tunneling oxide develops a high level of stress. As presently understood, this phenomena causes defects resulting in early or premature failures in the oxide during tunneling, thus further limiting the life of the device. No technique is known for thermally growing a low-stress tunneling oxide, while providing an oxide layer with substantially zero defects.
SUMMARY OF THE INVENTION
Briefly described, the present invention contemplates a method and means of depositing a tunneling oxide layer between two conductors with a low pressure, low temperature chemical vapor deposition (LPCVD) process. Preferably, tetraethylorthosilicate (TEOS) is used for this deposition process. Where the present method is used in an EEPROM device and polysilicon layers are used for forming the device, the deposited oxide is formed as follows. According to the present invention, a first layer of polysilicon is deposited and patterned as desired. A layer of silicon dioxide is then deposited by a decomposition of tetraethylorthosilicate to form a predetermined thickness of tunneling oxide on the surface of the polysilicon. The oxide layer formed from the deposited tetraethylorthosilicate is then thermally annealed and densified. Preferably, this is performed using a mixture of steam and an inert gas, such as argon, at a predetermined temperature. The process may be repeated where more than one tunneling layer is desired. Where necessary, prior to depositing the tetraethylorthosilicate, where enhanced emission structures are desired on the surface of the polysilicon, a layer of relatively thin oxide thermal oxide may be grown on the surface of the polysilicon.
Accordingly, it is an object of the present invention to provide a tunneling oxide in an EEPROM device which may be deposited with a low pressure chemical vapor deposition process.
It is another object of the present invention to improve the useful lifetime of an EEPROM device.
It is yet another object of the present invention to improve the yield in EEPROM processing.
It is another object of the present invention to improve the reliability of an EEPROM device.
It is yet another object of the present invention to produce a tunneling dielectric that is not limited by the underlying defect density of the material on which the oxide layer is being formed.
It is yet another object of the present invention to produce a tunneling dielectric having minimum stress.


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patent: 4599706 (1986-07-01), Guterman
patent: 4720323 (1988-01-01), Sato
patent: 4763177 (1988-08-01), Paterson
patent: 4763299 (1988-08-01), Hazani
patent: 4851370 (1989-07-01), Doklan et al.
patent: 4924437 (1990-05-01), Paterson et al.
Korma, E.J. et al. “SiO2Layers on Polycrystalline Silicon,” inInsulating Films on Semiconductors.J.F. Verweij and D.R. Wolters, eds., Elsevier Science Publishing Co., Inc, N.Y., N.Y. pp. 278-281.*
Peek, H.L., “The Characterization and Technology of Deposited Oxides for EEROM”, inInsulating Films on Semiconductors,J.F. and D.R. Wolters, eds., Elsevier Science Publishers B.V., 1983, pp. 261-265.

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