Depletion mode NAND string electrically erasable programmable se

Details Depletion mode NAND string electrically erasable programmable se Depletion mode NAND string electrically erasable programmable se

1995-08-21

1996-04-23

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518525, 36518527, 36518905, 36518906, 365195, G11C 1606

Patent

active

055110223

ABSTRACT:
A memory string for using in an EEPROM device is provided which has two selection transistors and a plurality of depletion-type floating gate transistors whose drain-source paths are connected in series with each other between two selection transistors. The EEPROM device comprises a memory cell array including a plurality of bit lines arranged in columns and a plurality of memory strings arranged in rows and columns, each of memory strings in the same columns connected between the corresponding bit line and the ground; a row decoder for selecting memory strings in the same row and supplying predetermined voltages to control gates to the floating gate transistors in the selected memory strings according to a program, erase or read operation; a column decoder for coupling the bit lines to a data line according to the operation mode; means for precharging unselected bit lines during the program operation to a predetermined voltage so as to prevent erase of unselected floating gate transistors; a program control circuit connected to the data line for supplying a program voltage to the selected bit line during the program operation; and means for grounding all bit lines during the erase operation.

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