Depletion controlled isolation stage

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

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257173, 361 56, H01L 2900

Patent

active

059259221

ABSTRACT:
An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.

REFERENCES:
patent: 4710791 (1987-12-01), Shirato et al.
patent: 4939616 (1990-07-01), Rountree
patent: 5010380 (1991-04-01), Avery
patent: 5012317 (1991-04-01), Rountree
patent: 5019888 (1991-05-01), Scott et al.
Ming, et al., "A CMOS VLSI ESD Input Protection Device, DIFIDW", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Digital Equipment Corp., Hudson, Mass., 1984, pp. 202-209.

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