Depleted sidewall-poly LDD transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257336, 257408, H01L 2976, H01L 2994, H01L 31062

Patent

active

058048561

ABSTRACT:
The present invention is directed to a metal oxide semiconductor transistor having a fully overlapped lightly doped drain (LDD) structure which offers the advantages of conventional fully overlapped LDD transistors but which significantly reduces the drain-to-gate overlap capacitance associate therewith. To achieve fully overlapped LDD construction and reduced drain-to-gate overlap capacitance, the metal oxide semiconductor transistor of the present invention employs a gate electrode comprising a main gate region formed from heavily doped polysilicon and depleted sidewall polysilicon spacers formed from undoped or depleted polysilicon. In the MOS transistor of the present invention, the lightly doped regions are fully overlapped by the combination of the depleted sidewall polysilicon spacers and the main gate region.

REFERENCES:
patent: 5418392 (1995-05-01), Tanabe

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