Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-27
2003-01-28
Tokar, Michael (Department: 2819)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06513148
ABSTRACT:
FIELD
This invention relates to the field of integrated circuits. More particularly this invention relates to methods for assigning coordinates to cells of logic trees of integrated circuits in a manner which maintains desirable cell density characteristics.
BACKGROUND
Microelectronic integrated circuits consist of a large number of electronic components, including individual logic devices or groups of logic devices that are applied to the surface of a substrate, typically a silicon wafer. The components are typically grouped to provide an application-specific integrated circuit. For each application-specific integrated circuit, placement of the components in optimum positions provides efficient layout of the components on the substrate in order to reduce manufacturing costs, processor delays, size and the like. Because the application-specific integrated circuits typically contain hundreds of thousands, if not millions of components, the task of optimizing the placement of components on a substrate surface is not practical without the aid of computers.
Computer aided designs are effective to provide component location on the substrate surface for minimizing interconnection distances, wire sizes, processing times and the like. The smallest component placed on a substrate surface is defined as a “cell.” A cell may be a single logic component of a larger logic tree or may be one or more logic trees. Assuming the number of cells N to be in the hundreds of thousands or millions, the number of different ways that the cells can be arranged on the substrate surface is equal to about N factorial. Selecting the optimum placement of the cells is therefore an extremely time consuming task.
Furthermore, despite the use of computer aided design techniques, algorithms used for selecting cell locations on the substrate surface may lead to cell congestion or overpopulation of cells in an area of the substrate surface. Overpopulation or overcrowding of an area of the substrate surface is undesirable from the standpoint of enabling efficient wiring routes, reducing overlapping circuits and the like. Accordingly, there continues to be a need for methods useful to further improve the cell placement on a substrate surface in order to lower substrate costs and increase processor speeds.
SUMMARY
The present invention relates to a method for selectively assigning coordinates to cells of a logic tree incorporated into an application-specific integrated circuit formed on a substrate surface. In a preferred embodiment, the method includes the steps of:
(a) determining coordinates of an old logic tree and performing an optimization of the old logic tree to obtain a new logic tree;
(b) determining coordinates for cells of the new logic tree which are connected to an output pin of the new logic tree
(c) determining coordinates for tree entrances to the new logic tree;
(d) determining coordinates for all cells of the old logic tree from the coordinates of the old logic tree determined in step (a),
(e) determining approximate coordinates for the cells of the new logic tree from the coordinates of the cells of a new logic tree connected to the output pin of the new logic tree determined in step (b) and the coordinates of the tree entrances to the new logic tree determined in step (c);
(f) sorting the approximate coordinates determined in step (e) based on the importance of each cell;
(g) determining optimized coordinates for each cell of the new logic tree based on the approximate coordinates of the new logic tree determined in step (e), the sorted approximate coordinates determined in step (f), and the coordinates of the cells of the old logic tree determined in step (d).
REFERENCES:
patent: 4607339 (1986-08-01), Davis
patent: 5774371 (1998-06-01), Kawakami
patent: 5859782 (1999-01-01), Scepanovic et al.
patent: 6026223 (2000-02-01), Scepanovic et al.
patent: 6031981 (2000-02-01), Lee et al.
patent: 6202194 (2001-03-01), Seningen et al.
patent: 6282693 (2001-08-01), Naylor et al.
patent: 6301693 (2001-10-01), Naylor et al.
patent: 6336209 (2002-01-01), Nishihara et al.
patent: 6370673 (2002-04-01), Hill
Gasanov Elyar E.
Postelga Youri P.
Zolotykh Andre J.
LSI Logic Corporation
Luedeka Neely & Graham
Mai Lam T
Tokar Michael
LandOfFree
Density driven assignment of coordinates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Density driven assignment of coordinates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Density driven assignment of coordinates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3014235