Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-04-14
2003-07-29
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S340000, C375S341000, C375S347000
Reexamination Certificate
active
06601213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a demodulator and to a communications system for use in wireless communications.
2. Description of Related Art
A method of improving the performance of a conventional receiver by incorporating coherent detection in the Viterbi decoder of the receiver is taught, for example, in “Viterbi demodulation with a phase tracking function” (Serizawa, Asakawa, and Murakami, The Institute of Electronics, Information and Communication Engineers B-II, Vol. J77-B-II No. 12, pp. 767-779, December 1994). This related art is described further below with reference to the accompanying figures.
A Viterbi decoder without a coherent detection function is described first as exemplary of the related art.
FIG. 18
is a block diagram of a receiver
200
comprising a conventional Viterbi decoder
220
. A coherent detector
210
first detects phase synchronization of a signal received by the receiver
200
, and then generates a recovered carrier phase synchronized to the received signal. The signal sign is determined based on the phase difference between the recovered carrier and the reception signal.
How the coherent detector
210
detects the signal sign is described next with reference to
FIGS. 19A and 19B
using by way of example a binary phase shift keying (BPSK) modulation method. In BPSK modulation, the code of a received signal is 0 if the absolute value of the phase difference between the recovered carrier and the received signal is less than or equal to &pgr;/2; if greater than or equal to &pgr;/2, the symbol is 1. That is, if the recovered carrier phase and the carrier phase of the received signal are the same, signals in the shaded area in
FIG. 19A
are 0, and all other signals are 1.
If we assume that the transmitter sends a 0, a signal will be received at reception signal point “a” under ideal, noise-free conditions. However, received signals are typically not received under such ideal conditions and are detected with some amount of noise. As a result, a signal that should be received with signal phase at point “a” may be received at point A due to this noise as shown in FIG.
19
A. If phase synchronization of the recovered carrier and the received signal is perfect, point A will remain in the shaded area even in this case and the signal will be correctly detected as a 0, thus not deteriorating the bit error rate characteristics.
In general, however, phase synchronization between the recovered carrier and the carrier wave of the received signal is not perfect due, for example, to the effects of phase shifting caused by fading in the typical channel of the mobile communications. For example, when the phase of the recovered carrier is different from the carrier wave of the received signal as shown in
FIG. 19B
due to fading, the above-noted point A will no longer be within the shaded area. The signal at point A will therefore be erroneously detected as a 1, and the bit error rate characteristics of the receiver is deteriorated. That is, if the carrier recovery circuit of the coherent detector does not generate a recovered carrier that is phase synchronized to the received signal, the bit error rate characteristics is likely to be deteriorated.
The operation of the above-noted coherent detector
210
is described next with reference to
FIG. 20
, a block diagram of the coherent detector
210
. As shown in
FIG. 20
, this coherent detector
210
comprises a multiplier
211
and carrier recovery circuit
212
. A received signal input to the coherent detector
210
is applied to the multiplier
211
and to the carrier recovery circuit
212
. The carrier recovery circuit
212
generates the recovered carrier as further described below. The multiplier
211
applies coherent detection using the received signal and the recovered carrier output from the carrier recovery circuit
212
.
Operation of the carrier recovery circuit
212
is described next below with reference to
FIG. 21
, a block diagram thereof. As shown in
FIG. 21
this carrier recovery circuit
212
comprises a doubler
212
a
, multiplier
212
b
, loop filter
212
c
, voltage-controlled oscillator
212
d
, PLL circuit
212
e
, and divide-by-two frequency divider
212
f
. The received signal input to the carrier recovery circuit
212
is doubled by the doubler
212
a
. By thus doubling the received signal, the doubler
212
a
obtains a constant phase regardless of the signal sign. That is, if the signal is 0, the signal phase is 0, and if the signal is 1, the signal phase is &pgr; with BPSK modulation. By doubling, therefore, signal phase is 0 and 2&pgr;, respectively, and matches.
Output from the doubler
212
a
is input to a PLL circuit
212
e
comprising multiplier
212
b
, loop filter
212
c
, and voltage-controlled oscillator
212
d
. Output from the PLL circuit
212
e
is a high SNR signal phase synchronized with the transmission signal carrier wave. The recovered carrier can thus be obtained by divide-by-two frequency division by the frequency divider
212
f.
A problem with the above-noted carrier recovery circuit
212
is the phase ambiguity with doubling. This is further described below with reference to the signal space diagrams in
FIG. 22A
to
22
D
FIG. 22A
shows a received signal distribution. In
FIG. 22A
the received signal will be distributed within the range of A if the sign of the transmitted signal is 0, and B if the sign is 1, as a result of noise. If the received signal is doubled, the output of doubler
212
a
can be represented by C in FIG.
22
B.
If the doubled signal is then input to PLL circuit
212
e
to increase the S/N ratio, the distribution range of PLL circuit
212
e
output will be narrowed as indicated by C′ in
FIG. 22C
due to noise. If the output of PLL circuit
212
e
is then frequency divided by two by the frequency divider
212
f
, the recovered carrier may be one of two states A′ and B′ in FIG.
22
D. That is, the recovered carrier has two stable points with indefinite phase offset 180°. It may therefore not be possible to correctly reproduce the carrier wave phase due to doubling by the carrier recovery circuit
212
.
In the case of BPSK modulation, the incorrect carrier wave phase will be shifted &pgr; from the correct carrier wave phase. Shifting the carrier wave phase in this way deteriorates the bit error rate characteristics. Various methods of solving this phase detection problem can be used to avoid this drop in performance, including differential coding, and carrier wave reproduction using a known pattern. Differential coding, however, invites a drop in the SNR, and methods using a fixed pattern invite a drop in transmission efficiency.
The coherent detector
210
in
FIG. 18
outputs to the Viterbi decoder
220
, the operation of which is described next below with reference to the block diagram thereof shown in FIG.
23
. As shown in
FIG. 23
, the Viterbi decoder
220
comprises a plurality of Viterbi decoding units
221
, comparison and selection circuit
222
, path metric memory
223
, and path memory
224
. It is to be noted that transition from state k to state m only in the Viterbi decoder
220
is considered below as operation is the same for other state transitions.
When a received signal is supplied to the Viterbi decoding units
221
at a particular symbol time, a branch metric is obtained by comparing the received signal with an ideal received signal, known as a replica signal, corresponding to a state transition. This replica signal is described next. Assuming a transition from state k to state m, the replica signal will be the signal output from the encoder when the transmission-side convolutional encoder changes from state k to state m. This value is uniformly determined by the convolutional encoder for each state, and is thus known to the receiver.
It is to be noted that the signal output when the transmitter's convolutional encoder changes from state k to state m is identical to this replica signal under ideal conditions free of noise and fading. In othe
Kojima Toshiharu
Uchiki Tatsuya
Baker Stephen M.
Birch & Stewart Kolasch & Birch, LLP
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Demodulator and communications system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Demodulator and communications system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Demodulator and communications system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3099624