Delta sigma PLL with low jitter

Details Delta sigma PLL with low jitter Delta sigma PLL with low jitter

1997-08-22

2000-03-28

Pham, Chi H.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1A, H03D 324, H03L 700

Patent

active

060441240

ABSTRACT:
A phase lock loop circuit for a digital radio generates the sampling frequency for sampling an incoming signal by storing the samples of the incoming signal in an accumulator at a first frequency. The accumulator is unloaded at the sampling frequency. A microprocessor monitors the rate in which the samples are stored in the accumulator and provides a switching signal to vary the sampling frequency in small increments to prevent the accumulator from overflowing or underflowing.

REFERENCES:
patent: 5021754 (1991-06-01), Shepherd et al.
patent: 5038117 (1991-08-01), Miller
patent: 5038120 (1991-08-01), Wheatley et al.
patent: 5256980 (1993-10-01), Itri
patent: 5517678 (1996-05-01), Klank et al.
patent: 5818303 (1998-10-01), Oishi et al.
"Fractional-N Synthesisers", Electronics World, Mar. 1996, pp. 196-199.
"Fractional-N Synthesis", Electronics World, Feb., 1996, pp. 130-135.
Riley, Tom A.D., et al "Delta-Sigma Modulation in Fractional-N Frequency Synthesis", I.E.E.E. Journal of Solid-State Circuits, vol. 28, No. 5, May 1993.
Best, Roland E., Phase-Locked Loops, Theory, Design and Applications., Chapter 3, pp. 136-153.

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