Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-11-08
2000-04-04
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711206, 711156, 711159, 711134, 711133, G06F 1210, G06F 1212
Patent
active
060473622
ABSTRACT:
An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. Virtual address spaces are allocated for processes respectively. Page table entries for translation of the virtual address spaces into physical addresses are not removed as processes terminate, but only after all virtual address spaces have been allocated.
REFERENCES:
patent: 4068303 (1978-01-01), Morita
patent: 4758951 (1988-07-01), Sznyter, III
patent: 4812969 (1989-03-01), Takagi et al.
patent: 4910668 (1990-03-01), Okamoto et al.
patent: 5301288 (1994-04-01), Newman et al.
patent: 5329627 (1994-07-01), Nanda et al.
patent: 5559980 (1996-09-01), Connors et al.
patent: 5899994 (1999-05-01), Mohamed et al.
Alexander David G.
Bragdon Reginald G.
Sun Microsystems Inc.
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