Delayed read/write scheme for SRAM interface compatible DRAM

Details Delayed read/write scheme for SRAM interface compatible DRAM Delayed read/write scheme for SRAM interface compatible DRAM

2001-11-14

2003-11-04

McLean-Mayo, Kimberly N. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000, C713S503000, C711S105000

Reexamination Certificate

active

06643732

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a SRAM interface compatible DRAM, and more particularly, to a method and a circuit for internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells where the dynamic memory cells require periodic refreshing.
(2) Description of the Prior Art
Dynamic or DRAM memory devices comprise an array of cells that typically comprise a single access transistor and a capacitor. By comparison, static or SRAM memory devices comprise an array of multiple transistor cells, typically comprising 4 or 6 transistors. For this reason, DRAM memory devices are significantly smaller, and therefore less expensive, than SRAM devices for the same memory capacity. However, SPAM devices have lower current consumption since the DRAM cell capacitors must be frequently refreshed to hold their memory state.
It is desirable, from a cost reduction standpoint, to use DRAM memory devices rather than SRAM devices. For example, it is desirable to replace the low power SRAM in a portable electronics system or cell phone with a DRAM to reduce chip or system size and cost. To facilitate the substitution of DRAM for SRAM, with minimal impact on performance, the DRAM device must overcome three problems. First, the internal refresh operations must be transparent to the external operations of the device. Second, the current consumption must be minimized, especially by eliminating unnecessary internal read/write operations. Third, the external access operations on the DRAM must be made compatible with those of a standard SRAM, and particularly the asynchronous SRAM, with very predictable results.
Referring now to
FIG. 1
, timing diagrams of the operation of a prior art DRAM memory device in a SRAM compatible condition are shown. Two operational cases are shown. In the bottom case, an external access is initiated when no internal or hidden refresh is pending. In the top case, a hidden refresh is pending when an external access of a memory location is initiated. In particular, referring to the lower or NO HIDDEN REFRESH case, the external address bus ADDRESS
22
transitions states to the address AD
2
. This transition is interpreted by the DRAM as an ACCESS REQUEST. Since no hidden refresh is pending in the DRAM, the asynchronous ACCESS REQUEST event is immediately executed as the ACCESS EXECUTE assertion of WL(AD
2
)
30
shows. Note that the access requires the minimum memory cell access cycle time for the DRAM core shown as the DRAM row access time plus the row pre-charge time, or T
ras
+t
rp
. Note that in the NO HIDDEN REFRESH case, the memory access operation, whether for a read or for a write, is executed immediately.
Referring now particularly to the HIDDEN REFRESH case, an internal refresh operation is pending as the asynchronous ACCESS REQUEST is made by the transition of ADDRESS
10
. The refresh will be executed as shown by the assertion of the REFRESH WL
14
. Therefore, the execution of the external access, ACCESS EXECUTE, shown by the assertion of WL(AD
2
) is delayed by the access time T
ras
+t
rp
. It can easily be seen that the differing response of the DRAM to the SRAM compatible address command causes a problem of indefiniteness. It is not possible for the external device, such as a microprocessor, to know in advance if a data read will be valid on the first cycle or the second cycle. This causes inefficiency in data access to the DRAM device because of this unpredictability.
Referring now to
FIG. 2
, another problem with using the DRAM as a SRAM compatible substitute is illustrated. In this case, an address skew condition occurs. In particular, the address bus ADDRESS
34
transitions first to the address AD
1
. Then ADDRESS
34
transitions to address AD
3
a very short time later. This condition is called address skew. In fact, the accessing device is making a single transition between a previous address AD
0
and the final address AD
3
. However, individual address lines may transition to the new address state at different times, perhaps due to different line lengths or capacitance coupling. In any event, the DRAM sees a preliminary address transition to AD
1
and interprets this as the beginning of an access. Note that the write enable bar line WE*
44
is in the read state. Therefore, the DRAM interprets the FALSE REQUEST as a read access of AD
1
. The read access of AD
1
is executed in the first read cycle as the DUMMY ACCESS shown on WL(AD
1
)
36
. When the final transition of ADDRESS
34
occurs to the address AD
3
, a second ACCESS REQUEST is generated. This read of AD
3
is executed on the second cycle as the ACCESS EXECUTE shown on WL(AD
3
)
40
. The ADDRESS SKEW case creates a dummy access of the DRAM that requires additional cycle time and unnecessarily consumes power.
Referring now to
FIG. 3
, yet another problem of the prior art usage of a DRAM in a SRAM compatible application is shown. In this case, a DUMMY READ is shown. The SRAM access specification calls for an address set up time T
as
on the ADDRESS line
50
prior to the write enable of the WE* line
54
. However, the DRAM will interpret the transition of the ADDRESS line
50
to AD
0
as the initiation of a read access from AD
0
. This access is executed in the first cycle as the FALSE READ ACCESS of WL(AD
0
)
58
. The assertion of the WE* line
54
is interpreted as a secondary request to then write to address AD
0
. This WRITE ACCESS is executed in the second cycle of WL(AD
0
)
58
. Once again, the performance of the memory is degraded by the inclusion of the unnecessary, and current consuming, false reads.
Several prior art inventions describe SRAM compatible DRAM methods and circuits. U.S. Pat. No. 6,028,804 to Leung discloses a circuit for creating a SRAM compatible DRAM. The circuit utilizes the access time for performing a refresh. In case of a conflict between an external access and an internal refresh, the external access is performed first. The refresh is performed second so that the external access is not delayed. U.S. Pat. No. 5,991,851 to Alwais et al describes a SRAM compatible DRAM device. A SRAM is used as a cache for the DRAM array. U.S. Pat. No. 5,999,474 to Leung et al teaches a SRAM compatible DRAM device using a SRAM cache and a DRAM array.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method and circuit for internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells wherein said dynamic memory cells require periodic refreshing.
A further object of the present invention is to provide a method and a circuit to make a DRAM memory array interface compatible with a SEAM memory array.
Another further object of the present invention is to provide a method and a circuit that reduces power consumption in a SRAM interface compatible DRAM memory array by eliminating dummy cycles.
Another further object of the present invention is to provide a method and a circuit that handles internal hidden memory refreshes without a throughput penalty.
Another further object of the present invention is to provide a method and a circuit that handles address skew and dummy read cycle by doing a refresh during a read/write wait time.
In accordance with the objects of this invention, a method of internally executing an externally initiated access to a dynamic memory array including a plurality of dynamic memory cells, wherein the dynamic memory cells require periodic refreshing, is achieved. The method comprises, first, determining if an external access to the dynamic memory array has been initiated. Second, a waiting period of RW idle time is inserted. The RW idle time comprises a sum of a row access time plus a pre-charge time. A pending refresh is performed during said RW idle time. A pending write access may be performed during the RW idle time. Finally, the external access is internally executed in the dynamic memory array after the RW idle

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