Delayed leaky write system and method for a cache memory

Details Delayed leaky write system and method for a cache memory Delayed leaky write system and method for a cache memory

2005-08-23

2005-08-23

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S135000

Reexamination Certificate

active

06934810

ABSTRACT:
A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated if the associated data signals are considered “leaky”. These data signals are flushed from the cache memory after a predetermined delay has occurred. The delay is provided to allow the IP to complete any subsequent requests for the same data before the flush operation is performed, thereby preventing memory thrashing. Pre-fetch logic may also be provided to pre-fetch the data signals associated with the requests. In one embodiment, the rate at which data signals are flushed from cache memory is programmable, and is based on the rate at which requests are processing for pre-fetch purposes.

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