Delay verification device for logic circuit and delay...

Details Delay verification device for logic circuit and delay... Delay verification device for logic circuit and delay...

1996-04-19

2001-11-13

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06317861

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay verification device for a logic circuit represented according to graph algorithms and a delay verification method therefor and, more particularly, to a delay verification device which is capable of conducting delay verification processing for a large-scale logic circuit at a high speed and a delay verification method therefor.
2. Description of the Related Art
One of the one conventional techniques related to delay verification of a logic circuit of this kind is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) No. Heisei 3-292573, entitled “Logic Design Verification System”. This literature recites a delay verification technique for converting initial design data regarding a logic circuit into a logic circuit, searching the converted logic circuit for signal paths from its input to its output to compute a delay time of each signal path, and comparing the delay time as a verification result with a preset standard delay time to modify the initial design data based on the determination results.
Because the above-described conventional logic design verification system automatically conducts all the processing for delay verification of logic initial design data as well as analyses and modification, accurate and efficient logic verification is possible without the operator's assistance.
The system, however, has a drawback that processing time is too long to verify delays of a large-scale logic circuit because the system conducts delay verification for the entire logic circuit whose delay time is to be verified.
Among other techniques regarding delay verification of logic circuits are, for example, those disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 64-66578, entitled “Delay Analysis System for Logic Circuit”, and Japanese Unexamined Patent Publication (Kokai) No. Heisei 2-231646, entitled “Delay Analysis System for Logic Circuit”. These literatures recite a delay verification technique for determining whether a path whose delay time exceeds a limiting value is a meaningless redundant path on a logic circuit according to the path activation method and removing a redundant path from a delay analysis result list according to the determination results to reduce a time required for determining whether a delay analysis result is good or bad and a technique for displaying only the components that are contributing factors to cause a delay time of a path to exceed a delay time limiting value to simplify modification.
The above-described conventional techniques have drawbacks that speed-up of delay verification after layout has a limit because none of these techniques makes the most of the delay state of a logic circuit prior to layout.
SUMMARY OF THE INVENTION
An object of the present invention is to eliminate the above-described conventional drawbacks and provide a delay verification device capable of conducting high-speed delay verification for even a large-scale logic circuit while making the most of delay results obtained prior to layout, and a delay verification method therefor.
According to the first aspect of the invention, a delay verification device for performing delay verification for a logic circuit may comprise:
circuit information storing means for storing circuit information on a logic circuit, a target for delay verification;
first delay information storing means for storing first delay information on a delay time between circuit elements predicted before layout designing of said logic circuit;
second delay information storing means for storing second delay information on a delay time between circuit elements computed after layout designing of said logic circuit in consideration of the designing results;
difference extracting means for comparing said first delay information and said second delay information to extract and register difference information on a portion, out of the components of said logic circuit, whose delay time of said second delay information is longer than that of said first delay information;
extracted circuit information obtaining means for searching paths of said logic circuit based on said circuit information and said difference information, extracting a path including a portion of said logic circuit corresponding to said difference information and storing the extracted path as extracted circuit information; and
delay analyzing means for analyzing delays of said logic circuit based on said extracted circuit information and said second delay information.
In the preferred construction, the circuit information storing means stores, as said circuit information, at least logic circuit information and delay information on a delay time of an arc corresponding to the internal part of a circuit element in question.
In another preferred construction, the first delay information storing means stores a delay time of an arc corresponding to a connection line between a circuit element and each terminal, which delay time is computed before layout designing of said logic circuit according to a predetermined relational expression based on information of an arc which is a flow of an electric signal between nodes including an external terminal of said logic circuit to be processed and a terminal of each circuit element, and the second delay information storing means stores a delay time of an arc corresponding to a connection line between a circuit element and each terminal which delay time is computed after layout designing of said logic circuit according to a predetermined relational expression based on said arc information of said logic circuit to be processed and the layout of said logic circuit.
In another preferred construction, the first delay information storing means stores a delay time of an arc corresponding to a connection line between a circuit element and each terminal, which delay time is computed before layout designing of said logic circuit according to a predetermined relational expression based on information of an arc which is a flow of an electric signal between nodes including an external terminal of said logic circuit to be processed and a terminal of each circuit element, the second delay information storing means stores a delay time of an arc corresponding to a connection line between a circuit element and each terminal, which delay time is computed after layout designing of said logic circuit according to a predetermined relational expression based on said arc information of said logic circuit to be processed and the layout of said logic circuit, the difference extracting means compares said first delay information and said second delay information to extract and register, as difference information, an arc whose delay time of said second delay information is longer than that of said first delay information, out of the arcs in said arc information of said logic circuit to be processed, and the extracted circuit information obtaining means searches, with respect to an arc extracted as said difference information, a path according to said circuit information stored in said circuit information storing means, extracts said arc as a circuit element, and a node and an arc as signal path elements on a signal path running through the arc and correlates the arc and node with the delay time of the arc to obtain extracted circuit information.
According to the second aspect of the invention, a delay verification method for verifying delays of a logic circuit may comprise the steps of:
a first step of storing circuit information on a logic circuit as a target for delay verification,
a second step of storing first delay information on a delay time between circuit elements predicted before layout designing of said logic circuit,
a third step of storing second delay information on a delay time between circuit elements computed after layout designing of said logic circuit in consideration of the results of the designing,
a fourth step of comparing said first delay information and said second delay information to extra

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