Delay time control circuit

Details Delay time control circuit Delay time control circuit

1999-12-15

2001-10-23

Lam, Tuan T. (Department: 2816)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C327S276000, C327S277000

Reexamination Certificate

active

06307403

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay time control circuit. Particularly, the present invention relates to a delay time control circuit capable of setting an amount of delay with high precision in a linear correspondence at both a leading edge and trailing edge of a pulse signal such as data and/or clock signal and, particularly, capable of setting an appropriate delay time for a write data in a CD-R/RW (CD-Recordable/Re-Writable) device.
2. Description of the Related Art
A data write speed of a recent CD-R/RW device has been increased remarkably.
The CD-R/RW device receives write data transferred from a host computer through an interface such as an SCSI (Small Computer System Interface) or an ATPI, EFM-modulates it and adds a modulated write data to a laser controller internally thereof. A laser light is on-off controlled for a write operation by the laser controller correspondingly to the EFM-controlled data and irradiates a predetermined track of a CD to form pits in the track to thereby write the data in the CD. The thus written data is read out by irradiating the track with a laser light controlled for read and receiving a light reflected from the pits by a light receiving element. The CD-R/RW device obtains the original data as a read-out data by demodulating the EFM-modulated signal received by the light receiving element and amplified by a read-out amplifier and transfers the read-out data to the host computer through the SCSI or ATPI.
In this case, in writing the EFM-modulated data in the CD, a length of a write time of the write data and a period of the data or the clock depends upon the write speed. Therefore, a timing regulation of the data or the clock becomes necessary. The timing regulation is performed by a delay circuit. In the case of the write operation of such as a CD-R/RW device, the timing regulation has to be performed with high precision. Furthermore, the timing regulation has to be performed by controlling the amount of delay at both a leading edge and a trailing edge of a pulse signal (1 bit) of such as the data or the clock signal with a preciseness corresponding to the write speed.
As shown in
FIG. 2
, a conventional delay time control circuit
10
for this purpose is constructed with a plurality of series-connected delay circuits Da to Dh, a selector
11
and a decoder
12
. The delay circuits Da to Dh provide an appropriate amount of delay corresponding to the number of the delay circuits starting from the first delay circuit Da having an input used an input terminal IN of the delay time control circuit
10
. The selector
11
receives outputs of the delay circuits Da to Dh, selects one of the outputs corresponding to a selection control signal SEL and outputs a signal having an aimed amount of delay with respect to the input signal at an output terminal OUT of the delay time control circuit
10
. The selection control signal SEL is produced by decoding data sent from a controller, etc., by using the decoder
12
. The selector
11
is constructed with AND gates and OR gates.
In the delay time control circuit
10
constructed with such AND gates and the OR gates, the gate operation when the signal input to the input terminal IN is HIGH level differs from that when the input signal is LOW level. Further, due to a difference between gate circuits, which operate in response to a selected output, it is impossible to select a total delay time in a linear relation. Therefore, a delay time in a leading edge of a pulse signal of one bit such as data or clock, etc., becomes different from that in a trailing edge thereof, causing a data error tend to occur.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a delay time control circuit capable of precisely setting a delay amount in both a leading edge and a trailing edge of a pulse signal in a linear correspondency and of easily setting a timing required by a related device with respect to an input signal.
In order to achieve the above object, a delay time control circuit according to the present invention is featured by comprising a delay circuit composed of 2
n
series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2, buffer circuits each connected to an output of each of the first and second inverters of the unit delay circuits of the delay circuit, 2
n−1
first connection lines each connecting between outputs of adjacent ones of the buffer circuits connected to the second inverters and 2
n−2
second connection lines each connecting between adjacent ones of the first connection lines, wherein, in response to an input signal input to the first inverter of first one of the unit delay circuits, an output signal delayed with respect to the input signal is obtained through one of the first connection lines and one of the second connection lines.
Assuming an inverter, to which a buffer amplifier is connected, an inverter preceding that inverter and a buffer circuit as a set of circuits, an output of the buffer circuit connected to the first connection lines and selected every other buffer circuit is produced by inverting an input signal to the preceding inverter twice, regardless of whether the input signal is “L” or “H”. Therefore, the delay time measured from the input of the input signal to the output of the output signal is substantially not influenced by the state of the input signal. Further, an output of any one of the buffer circuits, which is selected every other buffer circuit, is produced through the second connection line, which is connected to the first connection lines connecting the one buffer circuit of the second inverter, to the adjacent buffer circuit of the second inverter. Therefore, a delay time of an output signal obtained through a second connection line is substantially the same as that obtained through any other second connection line, so that the selection of delay time can be determined substantially by the number of buffer circuits of the second inverters selected as providing outputs.
As a result, it is possible to highly precisely set an amount of delay with respect to an input pulse signal in a linear relation at both a leading edge and trailing edge of the pulse signal.
According to another aspect of the present invention, a delay time control circuit comprises a delay circuit composed of 2
n
series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2, a three-state buffer circuit connected to an output of the second inverter of each unit delay circuit, connection lines for tournament-connecting the three-state buffer circuits of the unit delay circuits with using adjacent ones of the unit delay circuits as a unit and connecting an output of one of the three-state buffer circuits to an output terminal of the delay time control circuit and a buffer circuit connected to an output of the first inverter of each the unit delay circuit, the buffer circuit being equivalent to the three-state buffer circuit, wherein, in response to an input signal input to the first inverter of first one of the unit delay circuit, an output signal delayed by a predetermined amount with respect to the input signal is obtained through one of the tournament connection lines.
By constituting the delay circuit with a plurality of series-connected unit delay circuits each constituted with a pair of series-connected inverters and providing a circuit equivalent to a three-state buffer circuit in each unit delay circuit as a load, loads of the inverters of each unit delay circuit becomes equivalent. Therefore, an input of the unit delay circuit is inverted twice by these inverters. That is, when a signal “H” is input to the input terminal of the first inverter, it is inverted to “L” thereby and then inverted to “H” by the second inverter, which is output from the unit delay circuit. On the contrary, when a signal “L” is input to t

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