Delay settings for a wide-range, high-precision delay-locked...

Details Delay settings for a wide-range, high-precision delay-locked... Delay settings for a wide-range, high-precision delay-locked...

2006-04-11

2006-04-11

Tran, Khanh (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S158000

Reexamination Certificate

active

07027548

ABSTRACT:
A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.

REFERENCES:
patent: 5559476 (1996-09-01), Zhang et al.
patent: 5910741 (1999-06-01), Watanabe
patent: 5994934 (1999-11-01), Yoshimura et al.
patent: 6166572 (2000-12-01), Yamaoka
patent: 6208183 (2001-03-01), Li et al.
patent: 6239634 (2001-05-01), McDonagh
patent: 6346839 (2002-02-01), Mnich

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