Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-24
2001-10-23
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06308306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay route searching technique for logical circuits including LSIs, and more particularly to a delay route searching technique capable of reducing the process time and the storage capacity needed for the processing of delay route searching.
2. Description of the Related Art
When designing a logical circuit such as an LSI, it is necessary to search for any delay route and find out whether or not there is a logical path failing to satisfy the design standard on delay time. In doing so, if it is tried to individually assess the delay time of every logical pass in the logical circuit, tracing of the same route is often duplicated, taking an unnecessarily long processing time.
In order to solve this problem, the following method has been proposed (for instance as disclosed in the Japanese Patent Laid-open No. Hei 6-119411). This method will be described below with reference to
FIG. 9
, wherein reference signs A and B denote starting points; X and Y, end points; and G
1
through G
4
, components positioned between the starting points and the end points.
By this method, first regarding component G
1
, the worst delay time TA
1
from starting point A is figured out, and so is the worst delay time TB
1
from starting point B at the same time. In this context, the longest delay time is deemed to be the worst delay time. After that, as information on component G
1
, as illustrated in
FIG. 10
, the identifier of starting point A, the delay time TA
1
and the identifier of the immediately preceding component (starting point A in this case) on the route where the worst delay time occurs are stored in coordination with one another, and at the same time the identifier of starting point B, the delay time TB
1
and the identifier of the immediately preceding component (starting point B in this case) on the route where the worst delay time occurs are also stored in coordination with one another.
Next, component G
4
is subjected to similar processing, and such information as listed in
FIG. 11
is stored as information on component G
4
. TB
4
denotes the worst delay time between starting point B and component G
4
.
Then, regarding component G
2
, the worst delay time TA
2
from starting point A is calculated, and so is the worst delay time TB
2
from starting point B at the same time. The abovementioned delay time TB
2
is figured out by adding the delay time TB
4
stored as information on component G
4
and the delay time T
42
between components G
4
and G
2
. After that, such information as listed in
FIG. 12
is stored as information concerning component G
2
.
Next, regarding component G
3
, the worst delay time TA
3
from starting point A is figured out, and so is the worst delay time TB
3
from starting point B at the same time. The worst delay time TA
3
is figured out in the following manner. The already stored worst delay time TA
1
(see
FIG. 10
) from starting point A to component G
1
and the delay time T
13
between components G
1
and G
3
are added (TA
1
+T
13
), and the already stored worst delay time TA
2
(see
FIG. 12
) from starting point A to component G
2
and the delay time T
23
between components G
2
and G
3
are added (TA
1
+T
23
). After that, the two sums are compared, and the greater sum is supposed to be the worst delay time TA
3
from starting point A. Now, if (TA
1
+T
13
) is found smaller than (TA
2
+T
23
) for instance, the worst delay time TA
3
from starting point A to component G
3
is (TA
2
+T
23
). The worst delay time TB
3
from starting point B to component G
3
(which in this case is supposed to be TB
4
+T
42
+T
23
) can be calculated n the same manner. After that, such information as listed in
FIG. 13
is stored as information on component G
3
.
End points X and Y are also subjected to similar processing, and information on these end points X and Y, such as shown in
FIGS. 14 and 15
, respectively, is stored.
By comparing the delay times in the information on end points X and Y shown in
FIGS. 14 and 15
, respectively, with the pertinent design standard on delay time, it can be found out whether or not there is any logical path violating the delay standard. Further, by using the identifier of the immediately preceding component included in the information shown in
FIGS. 10 through 15
, the logical path having the worst delay time can be identified.
According to the prior art method described above, since no duplication occurs in the tracing of routes, the processing time can be shorter than in the case where the delay time on every logical path in the logical circuit is individually figured out.
However, the above-described method according to the prior art, which needs the storage of information on each component and each end point with respect to every starting point (the worst delay time from the starting point, and the immediately preceding component), entails the problem of requiring a large storage capacity. Moreover, since it is needed to calculate the worst delay time for each component and each end point with respect to every starting point, the processing time cannot be reduced substantially. Although the logical circuit illustrated in
FIG. 9
has only two starting points, an actual logical circuit, such as an LSI, may have dozens of starting points, necessitating a much greater storage capacity and a much longer processing time.
Besides the technique described above, the prior art includes another proposed technique, by which pre-layout-design delay information and post-layout-design delay information, for example, are compared, arcs for which the delay time in the post-layout-design delay information is longer are detected, and delay analyses are conducted only of routes involving the detected arcs (e.g. the Japanese Patent Laid-open No. Hei 9-6836). This technique, however, involves the problem that it is applicable only where pre-layout-design delay information and post-layout-design delay information are available.
SUMMARY AND OBJECT OF THE INVENTION
An object of the present invention, therefore, is to make it possible to reduce the processing time and the storage capacity required for searching delay routes without having to make available any special information.
In order to achieve the above-stated object, a delay route searching method for logical circuits according to the invention comprises:
a fan-out direction delay time calculating step to calculate the transit time from at least one component as a starting component, which is a starting point in a group of components constituting a logical circuit to be subjected to delay route searching, to the other components as target components, and to store the name of each of the target components and the worst one of all the calculated transit times with respect to that target component;
a fan-in direction delay time calculating step to calculate the remaining time to at least one component as a ending component, which is an end point in the group of components constituting the logical circuit to be subjected to delay route searching, from the other components as target components, and to store the name of each of the target components and the worst one of all the calculated remaining times with respect to that target component;
a delay analysis non-needing component identifying step to add the worst transit time stored at said fan-out direction delay time calculating step to the worst remaining time stored at said fan-in direction delay time calculating step with respect to each target component, to compare the result of each such addition with a design standard delay time, and to ,if the addition result is not larger than the design standard delay time, determine as a free-of-delay-analysis component the target component on which that addition result has been obtained; and
a delay analysis non-needing component-reflecting delay route searching step to perform delay route searching on the routes except for all the routes involving the free-of-delay-analysis
NEC Corporation
Phan Trong
Young & Thompson
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