Delay phase-locked loop device and clock signal generating...

Details Delay phase-locked loop device and clock signal generating... Delay phase-locked loop device and clock signal generating...

2007-07-10

2007-07-10

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S371000, C375S354000

Reexamination Certificate

active

10365179

ABSTRACT:
A PLL device of a core logic chip includes a controlled delay circuit having a plurality of controlled delay lines interconnected in series and outputting therefrom a plurality of output clock signals in response to a reference clock signal; a phase detector for generating an adjusting signal according to a phase difference between the reference clock signal and the output clock signals; and a control circuit for asserting a plurality of control signals to the controlled delay lines, respectively, according to the adjusting signal in order to have the delay times of the output clock signals independently adjusted and outputted again by the controlled delay lines. The delay times of the output clock signals can be determined according to a distribution table and further tuned according to a circuitry and a layout of the core logic chip.

REFERENCES:
patent: 5633608 (1997-05-01), Danger
patent: 5838204 (1998-11-01), Yao
patent: 6044122 (2000-03-01), Ellersick et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6147561 (2000-11-01), Rhee et al.
patent: 6326826 (2001-12-01), Lee et al.
patent: 0460274 (1990-11-01), None
patent: 1146641 (2001-10-01), None

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