Delay model circuit for use in delay locked loop

Details Delay model circuit for use in delay locked loop Delay model circuit for use in delay locked loop

2005-09-13

2005-09-13

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C327S158000

Reexamination Certificate

active

06944833

ABSTRACT:
A delay model circuit for use in a delay locked loop (DLL) of a semiconductor device. The delay model circuit includes a first delay circuit for providing a first delay amount; a second delay circuit having N number of delay load blocks, each having a different load delay amount from others, N being a positive integer; an adjustable load control circuit for generating an adjustable load control signal; and a switching circuit for selectively coupling at least one delay load block to the first delay circuit in response to the adjustable load control signal to thereby allow the delay model circuit to provide a negative delay as a combination of the first delay amount and a second delay amount provided by the selected delay load block.

REFERENCES:
patent: 6212126 (2001-04-01), Sakamoto
patent: 6301190 (2001-10-01), Tsujino et al.
patent: 6339553 (2002-01-01), Kuge
patent: 6504408 (2003-01-01), von Kaenel
patent: 2001/0015927 (2001-08-01), Ooishi
patent: 2000-065902 (2000-03-01), None
patent: 2001-195899 (2001-07-01), None

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