Delay-matched ASIC conversion of a programmable logic device

Details Delay-matched ASIC conversion of a programmable logic device Delay-matched ASIC conversion of a programmable logic device

2006-05-02

2006-05-02

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C716S030000, C716S030000

Reexamination Certificate

active

07038490

ABSTRACT:
An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic blocks corresponding on a one-to-one basis with logic blocks in the PLD and a routing structure corresponding to the programmable routing structure of the PLD. Vias or traces are selectively placed in the ASIC so that logical behavior of its logic blocks matches that implemented in the PLD and the signal propagation delay through the ASIC matches the delay through the PLD.

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PGA Data Book, Oct. 1996, Masked Array Conversion For ORCA (“MACO”), Lucent Technologies Inc., p. 7-7.

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